Hi all!
Sorry if I'm double posting here but couldn't seem find a simple answer to this one while searching and a bit unsure about what the d/s really has to say in this subject.
In wonder, can the tas5706b recreate the master clock from the bit clock using internal PLL in order for me to use only but a simple 3-wire i2s protocol consisting of only data, lrck and bck?
Thank you!