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TAS5756M question on switching frequency

Other Parts Discussed in Thread: TAS5756M

May I know how to set the switching frequency for the TAS5756M? By Hardware or by setting register?

I try to put 6.3V, 3.5V, 2.8V, 2.3V, 2.0V on SPK_GAIN/FREQ pin of TAS5756 and also try change register P0-R34 Switching frequency speed Mode[1:0] to 00, 01. or 10. 

But the output signal(SPK_OUTA+ to GND) frequency is still keep on the same on around 141kHz ( Mono(PBTL) system application )

  • Raymond,

    The only required change for switching frequency and gain is via hardware, SPK_GAIN/FREQ pin. Reference table 15 on page 53 of datasheet. To see the gain and switching frequency change, state of the SPK_GAIN/FREQ pin must be set prior to powering up the device. The device has to be powered down and powered up for the gain and/or frequency change to take effect.

  • Damian,

    There is a clock error in yesterday test result. (PLL unlock is detect)

    With clear the issue, the current situation is the output signal(SPK_OUTA+ to GND) frequency is still keep on the same on around 288kHz ( Mono(PBTL) system application ) after setting the voltage 2.0~5.8V of SPK_GAIN/FREQ pin (It will not work when voltage >6.6V)

    1./It seem Fsync is related to the clock setting, will my clock affect the switching frequency?

    There is a 32bit 48kHz sampling I2S signal input 

    SCLK: 3.072MHz

    LRCK: 48kHz

    SDIN: I2S Data 32 bit stereo

    MCLK: signal keep at logic low

    Using Clock Slave Mode with SLCK PLL to Generate Internal Clocks (3-Wire PCM)

    J=12, D= 0000, P = 1, R=2, NMAC = 2, NDAC=12, DOSR = 8, NCP=4, P0-R34 16x Interpolation [4] (R/W) = 0

    2./Also I would like to check P0-R13 PLL Reference[6:4],  is 001 represent The PLL reference clock is SCLK?

    3./ I got confused information from below register, are both register mean PLL is locked? (P0-R37 Ignore PLL Lock Detection [0] (R/W) set to 0)

    -P0-R4 PLL Lock Flag [4] (Read Only) 0 The PLL is locked

    -P0-R94 Clock Detector Status 5 [5] (Ready Only) 0 PLL is unlocked 

    Raymond

  • Hello Raymond,

    1. Yes Fsync is related to LRCLK frequency. See table 14 and 15 on page 53 of datasheet.
    2. P0-R13 [6:4] = 001 means SCLK is the PLL reference clock, d/s is incorrect (good catch).
    3. According to the d/s that's correct. Let me verify it.
  • Hi Damian,

    Damian Lewis said:

    Hello Raymond,

    1. Yes Fsync is related to LRCLK frequency. See table 14 and 15 on page 53 of datasheet.
    2. P0-R13 [6:4] = 001 means MCLK is the PLL reference clock.
    3. According to the d/s that's correct. Let me verify it.

    1. So if LRCLK frequency is 48kHz, Fsync should be 96kHz?
    2. When P0-R13 [6:4] = 001 means MCLK is the PLL reference clock., what does 000 mean (it also state MCLK is the PLL reference clock. in datasheet)
    3. I will wait your result

    Raymond

  • Raymond,

    Sorry for the confusion. I meant When P0-R13 [6:4] = 001 means SCLK is the PLL reference clock (good catch). I will get back to you on that #3, but you can check it on your EVM and let me know your findings.

  • Hi Diamen,

    Thanks for verify.

    1./ I rework on my hardware & software.As the result I find that the switching frequency is 4xFsync, 5xFsync,6xFsync & 8xFsync for 48kHz sampling rate instead of 2x, 4x 6x 8x in datasheet, Is it normal?.

    2./ I double check again P0-R4[4] is 0 (PLL is locked) and P0-R94[5] is 0 (PLL is unlocked). But I get this contradiction information at the same time. if P0-R94[5] is 0 also mean PLL is locked?

    Raymond

  • Raymond,

    1. You're correct. It should be 4x, 5x, 6x and 8xFsync (384, 480, 576 and 768kHz). The d/s table is incorrect. I will request that it's corrected.
    2. P0-R94[5] = 0 means PLL is locked. Again the d/s is incorrect and I'm requesting that it's fixed.
  • Hello


    What is the required power sequence (timing 3.3V to PVDD, minimum rise times)?

    Since GVD is regulated from PVDD how can SPK_GAIN voltage be correct before powering up the device?

    Here is my power up, 1= 48V input, 2=25V PVDD, 3=3.3V, 4=GVD. Is it ok?

  • Hi Eric,

    Next time please make a new post for your question and don't reply to an old post, which doesn't directly apply to your question. Your questionis on power up sequence. There's no power up sequence required for TAS5756M with respect to PVDD and 3.3V. GVDD will follow PVDD until it reaches it's regulated voltage. It's hard to see from your scope capture due to the different voltage scales used for PVDD and GVDD.

    The power up sequence you have looks fine.