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TAS5624A Behavior of FAULT pin

Other Parts Discussed in Thread: TAS5624A, TAS5624

Hi,

We understood that FAULT pin is asserted to low when detecting OTE, OLP, and UVP.
So, FAULT pin slowly changes to low from around 80℃(Ta) at the high temperature evaluation.
Could you please tell us the reason for this phenomenon?

Best Regards,
Kato

  • Kato-san,

    Was the eval done on a EVM or can it be duplicated on an EVM? I assume only FAULTz=L and OTWz still H?

    What is the operation condition during the eval? PVDD, Po, Load, etc.

    Thanks.

    reg,

    Paul.

  • Hi Paul-san,

    Thank you for your response.
    Our customer used his test board which he designed, evaluated that.
    I will confirm the evaluation condition to him and will get back with you.

    Best Regards,
    Kato

  • Hi Paul-san,

    The evaluation condition is shown as below.
    In addition, OTW pin remained high when FAULT pin was low.
    Could you please tell me why FAULT pin slowly changes to low?

    <The Evaluation Condition>
    PVDD : 25V
    Input Audio Source : Music
    Pout : Clipping Output(THD=5%)
    Load Structure : BTL
    Load Impedance : 6Ω
    Modulation Mode : BD Mode

    Best Regards,
    Kato

  • Hi Paul-san,

    Please let me know as I send the customer's schematic to your private e-mail if you need that.

    Best Regards,
    Kato

  • Hi Paul-san,

    I will inform additional information.
    The resistor of 33kohm is connected  between OC_ADJ and GND as the over-current programming resistor.
    Please let me know the cause of this FAULT behavior.

    Best Regards,
    Kato

  • Hi Kato-san,

    I think you are on the right path. It looks like it could be OC protection. Have they tried with 24K ohms OC_ADJ resistor? If it is OC, you can observe the CBC (cycle by cycle) protection kicks in on the PWM output waveform. After OC reaches the over load protection counter, then the device will be SDz and Faultz pulled low. 

    Also I 'd suggest checking the heat sink and thermal interface material used. Make sure the thermal design is good. 

    reg,

    Paul.

  • Hi Paul-san,

    Thank you for your advice.
    The output MOSFETs were not Hi-Z although the FAULT pin was asserted low in that case.
    So, I believe that TAS5624A operates between CBC protection and OLP protection, that is CBC protection <= 2.6ms.
    Is my understanding correct?
    In addition, could you please tell me the detailed operation of output MOSFETs in CBC protection?
    For example, could you please send the evaluation result to me if you have?

    Best Regards,
    Kato

  • Hi Paul-san,

    I have an additional question.
    It seems the CBC protection is related to the junction temperature of TAS5624A since that phenomenon does not occur at the room temperature.
    So, could you please tell me the detection principle regarding the CBC protection?

    Best Regards,
    Kato

  • Kato-san,

    Here is a short description of Cycle By Cycle Current Control.

    CBC means that the OC protected MOSFET will remain turned off within the PWM cycle where the OC event happened.

    At the first following rising edge PWM the MOSFET will be turned on again. CBC OLP counter is based on the PWM switching freq of 384KHz.  The counter decreases on every n’th non-OC PWM cycle and increased on every m’th OC cycle.

    When counter reached 1000 count the OLP will kick in and shut down the affected channel. With 384KHz PWM freq, 1000th count correspond to 2.6mS minimum.

    reg,

    Paul.

  • Hi Paul-san,

    Thank you for explaining so politely.
    I understood that sequence to change from the CBC protection mode to the OLP protection mode.
    So, could you please tell me the timing when FAULT pin are asserted low and that relation of the junction temperature for the CBC protection?
    I would like to confirm whether that timing should be during the CBC protection or the OLP protection.

    Best Regards,
    Kato

  • Hello Kato-san,

    I hope you do not mind me jumping in here with a comment. I was one of the designers of the TAS5624 series. One thing that happens with a 33K Ohm ROC resistor is that there is a bit of uncertainty of which mode (latched OC or CycleByCycle) that occurs. This uncertainty depends upon temperature, so it would be possible to be in latched mode at some normal operating temperature,  then switch into CBC mode at a higher temperature like 80C. When the part switches over into CBC mode, the current limiting threshold will drop significantly, and after some time the OLP counter will trip and the fault pin will go low. Lower ROC resistors eliminate this uncertainty and keep the part in CBC mode, and raise the limting threshold compared to 33K as well.

    If you want to see whether this is happening, you could apply a short to ground with something like a 1 Ohm load ressitor and see how long the part takes to shut down at 30C, then do the same thing at 80C. If you are in latched mode at 30C, you would see almost immediate activation of the fault. If you are in CBC mode at 80C, it would take ~2-3ms to shut down.

    Paul Chen has the right idea, to use a lower value of ROC (like 24K) to raise the CBC threshold and make sure you are not current limiting when you don't want to.

  • Hi Jeff-san,

    Thank you for explaining so politely.
    I will inform our customer of your information that the over-current threshold programming resistor should be replace 33kΩ to 24kΩ to increase this OC limiting threshold.
    By the way, could you please tell me why FAULT pin slowly is asserted to low?
    Actually, this transition time was about 1 ~ 2minutes at 80℃.

    Best Regards,
    Kato

  • Hi Kato-san,

    It sounds very unusual for the /FAULT pin to drop slowly in amplitude. It should either be high or low, since it is an open drain digital output. Did you observe an average voltage with a meter or other slow responding instrument? It might actually be toggling if there is a self-resetting fault, such as under voltage protection. I would not expect to see that behavior for any latched fault, such as OTP or OLP, unless your customer has set up an auto-reset circuit.

    The duty cycle of the toggling would tend to look like a slowly changing voltage, on average. You might be able to see this toggling on an oscilloscope. There is UnderVoltageProtection for PVDD, VDD, and AVDD. It would be unusual to see UVP for AVDD, unless something were powered externally from that pin.

  • Hi Kato-san,

    I thought of one other possible explanation for having a temperature dependence of UVP. In addition to AVDD and PVDD, the UVP operates on the 12V pins GVDD_AB, GVDD_CD, and VDD. In the design, we may have increased transient current in GVDD_AB and GVDD_CD as the temperature rises under high current conditions, such as the 5% THD condition you mentioned. If the customer used some resistance, like 3 Ohms or more in series with the GVDD_AB or GVDD_CD pins, it could result in intermittent UVP conditions. I have seen cases where the resistors were partially damaged and had maybe 50 ohms in series, so they caused trouble occasionally. Please ask your customer to check the value of any such resistors, and try shorting them as an experiment.

  • Hi Jeff-san,

    Thank you for your quick response.
    Our customer has not probed PVDD_xx and GVDD_xx although he has verified the CBC limiting protection using the oscilloscope, he has confirmed that the voltage of VDD pin has worked properly.
    So, I will inform him of it.
    Then, the resistors of 3.3Ω have been connected between those pins of GVDD_AB, GVDD_CD, and VDD and the 12V power line, he will confirm whether the value of those resistors is appropriate just in case.
    I will contact to you if I have the additional questions.

    Best Regards,
    Kato