• State TI Thinks Resolved
  • Locked Locked
  • Replies 2 replies
  • Answers 1 answer
  • Subscribers 28 subscribers
  • Views 545 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DRV612 Gain-Setting

KANJI SHIBATANI
Mastermind 6205 points
Other Parts Discussed in Thread: DRV612

Hello

In the DRV612 D/S p10, Gain setting is latched during power on.

Would you please let me know more detail

Q1   How is  the gain  latched in regard to VDD voltage and the time. 

 For example VDD is more than XX volt  and then within YY ms.

Q2   Do you have any restriction about VDD ramp up? i.e. VDD should be ramp up within ZZ ms,

and should be no glitch.

My client had 3pcs/1500pcs gain error (+3.5dBsetting(GOOD)<=>+16dB(BAD)) and they are

worried about for their production stop.

I hope your answer within 2 days

With my best regards

 

  • 0
    TI__Mastermind 37045 points

    Hi, Kanji-san,

    The gain is set when the VDD voltage reaches 2.8V.

    Have the tried to put the "bad" parts on the EVM to make sure that it is not related to their PCB?

    reg,

    Paul.

  • 0 in reply to user5276421
    Mastermind 6205 points

    Hello Chen-san

    Thank you for your reply!

    *New(Good) parts were replaced, and there are no issue. So, this in not related to their PCB.

    *I understand that in case Vdd reaches to 2.8V, Gain setting is latched.

    However  I think this  2.8V  is typical value.  

    Don't you think 2.8V should be different +/-10% and so on depends on each device?

    Please let me know  about the torelance of  2.8V.

    I heard from client that  Vdd may be have some small glitch at the point of 2.6V.( please refer attached)

    I think this may be the cause.....

    Best Regards