TAS5624A Power Supply Voltage that PWM Duty Cycles of Input and Output are Same

Sadanori Kato

Other Parts Discussed in Thread: TAS5624A

Hi,

Could you please tell us the power supply voltage that the pwm duty cycles of input and output matches although the closed-loop is adopted in TAS5624A, those does not match in the normal operation?
We do not mind even a design expected value if the power supply voltage is over the recommended value.

Best Regards,
Kato

over 9 years ago

0 Tuan over 9 years ago

TI__Mastermind 33420 points

Hello Kato-san:

I've asked my colleague to help answer your question. He may need more information like load impedance and power required.

Best regards,

Tuan

0 Sadanori Kato over 9 years ago in reply to Tuan

Guru 36490 points

Hi Tuan-san,

Thank you for your response.
The condition is shown as below.
I am looking forward to hearing from you.

Pout : ~60W(the unclipped output voltage)
Rload : 6Ω
PVDD_X : 28V
Output Configuration : BTL

Best Regards,
Kato

0 sorenpoulsen over 9 years ago in reply to Sadanori Kato

TI__Intellectual 1560 points

Kato-san,

You are right that the output duty cycle is a function of PVDD (when M>0, D<>50%) due to the constant input modulation index to outpt voltage transfer function.

The device is designed to have a stable closed loop operation, which requires the output modulaiton index to be larger than the input modulation index. In fact, PVDD needs to be increased to above the device abs. max. rating to achieve equal input and output PWM duty cycles, which is not advicable.

0 Sadanori Kato over 9 years ago in reply to sorenpoulsen

Guru 36490 points

Hi Soren-san,

Thank you for your advice.
Could you please give me your advice as below if I have any misunderstanding?

<Condition>
Input Signal : 0dBFS
Gain for SE mode : 0.4264
Volume Level : 0dB
Modulation Level : 50%

Output Voltage = 1(0dBFS) * 1(0dB) * 0.4264(Gain) * 50(Modulation Level) = 21.32Vrms

So, I believe that approximately 120.60V is necessary as the power supply voltage to match the pwm duty cycles of input and output for the open-loop architecture.
(PVDD_X : 21.32Vrms * 2 * SQRT(2) * 2 = 120.60V)

Best Regards,
Kato

0 Sadanori Kato over 9 years ago in reply to Sadanori Kato

Guru 36490 points

Hi Soren-san,

This issue has been closed by the following information.
Thank you for your support.

http://e2e.ti.com/support/amplifiers/audio_amplifiers/f/6/t/381495.aspx

Best Regards,
Kato

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TAS5624A Power Supply Voltage that PWM Duty Cycles of Input and Output are Same