TAS5766M PLL won't stay locked

James Moscola

Other Parts Discussed in Thread: TAS5766M

As the subject mentions, I'm using a TAS5766M and the PLL won't stay locked. I'm currently using one of the GPIO pins to monitor the state of my PLL and another GPIO pin to monitor the state of the "clock invalid" value. My PLL locks, but briefly unlocks about every 1.5 seconds. After a short blip, my PLL locks again. About 1.5 seconds later it unlocks again. No audio is output from the device. However, each time the PLL blips my speaker pops. Some pops are very quiet. Others are quite a bit louder.

I'm supplying a TAS5766M with I2S using a 3-wire configuration.
I've configured SRCREF (Page0,Reg13,D[6:4]) to use BCK as the reference clock for the PLL.

The BCK signal is running at ~2.8 MHz.
My sample rate and LRCLK are running at 44.1 kHz.
My I2S source is configured to send 32-bit words.

I've configured my TAS5766M according to Table 8 of the device data sheet (page 25).
More specifically, I've configured the device using the values for 44.1 kHz with an RSCLK of 64.

Reading some registers, I can see the following errors in registers 91, 94, and 95:
Reg 91: error on SCK ratio
Reg 94: SCK is halted
Reg 95: SCK halt has occurred.
I assume that I can ignore these errors since SCK is not present.

Any tips on what might be causing my PLL issues or suggestions on how to debug further would be greatly appreciated.

Thanks,
James

over 8 years ago

0 J- over 8 years ago

TI__Mastermind 46195 points

Hi James,

The BCLK and WCLK frequencies you use match Table 4, in page 22 of the TAS5766M datasheet, so in that sense it seems correct.

One trick to make your configuration simpler is to simply configure the part as follows:
P0_R13 = 0x10 (PLL reference clock = BCK)
P0_R37 = 0x08 (Ignore SCK halt detection)

...and leave the rest of the registers default.

Things to watch for:
1. Make sure all parameters in Figure 35 are met (TAS576xM Serial Audio Timing – Slave). We've seen cases where tlb and tbl parameters were not met due to board delays between BCK and LRCK causing issues. If your apps processor (or MCU) has drive control on the I2S pins, experiment with that. If you have series resistors on the I2S bus, try replacing them with 0-ohm for debug.
2. Make sure BCK and LRCK are in sync and do not drift.
3. Is the clock jittery? If so, perhaps you might consider setting the part as I2S master and using an on-board xtal+osc.

Regards,
J-

0 James Moscola over 8 years ago in reply to J-

Prodigy 50 points

Thanks for the response. I tried the simple configuration that you suggested but it failed. I easily meet all the timing requirements form Figure 35 of the data sheet. I suspect the clock is too jittery for the PLL to lock.

As per your suggestion, I decided to try setting up the TAS5766 as the I2S master. I only had a few crystals laying around with which I could test so I selected a 13,521,270 Hz crystal and built a simple oscillator circuit.

Using the 13,521,270 Hz crystal, I configured the PLL as follows:

P = 1
R = 1
J = 6
D = 6796
=========
13,521,270 Hz * 6.6796 = 90,316,675 Hz

Now, the PLL seems to lock with no problems at all. Additionally, my audio source is transmitting audio data to the TAS5766. Sadly, I’m still not getting anything more than random pops from the speakers that I have connected.

I do have some questions regarding the TAS5766 in I2S master mode that might help clarify things. Figure 34 (page 23) of the data sheet shows SCK as the input into the BCK divider. Since my SCK is coming from my 13,521,270 Hz crystal, it is impossible to compute the 2.88 MHz BCKO signal that I want for my I2S slave (64 * fS mode). Additionally, it is impossible to compute the 44.1 kHz that I need for my LRCKO signal from BCKO.

Does the TAS5766 allow me to use the output of my PLL (either PLLCK or MCK) as the input to my BCK divider? If not, what is TI’s recommended approach for generating the appropriate output frequencies for BCKO and LRCKO?

I’ve included the register settings that I used for my initial test of the TAS5766 in I2S master mode.

================
PAGE 0 Registers
================
0x04 = 0x01 enable PLL

0x07 = 0x01 STDOUT is pre-processed I2S
0x08 = 0x2C set GPIO 1,2,3 as output
0x09 = 0x11 set BCK and LRCLK as outputs for master mode

0x0C = 0x03 BCK and LRCK dividers are functional
0x0D = 0x00 PLL reference clock is SCLK

0x14 = 0x00 P = 1
0x15 = 0x06 J = 6
0x16 = 0x1A D = 6796 (most significant 6-bits)
0x17 = 0x8C D = 6796 (least significant 8-bits)
0x18 = 0x00 R = 1

0x1B = 0x01 DDSP = 2
0x1C = 0x0F DAC clock divider : NDAC = 16
0x1D = 0x03 NCP clock divider : NCP = 4
0x1E = 0x07 OSR clock divider : DOSR = 8

0x20 = 0x03 BCK divider (BCKO = 13,521,270 / 4 = 3,380,317 Hz)
0x21 = 0x3F LRCK divider (LRCKO = 3,380,317 / 64 = 52,817 Hz)

0x23 = 0x04 DSP clock cycles available per audio frame (MS bits)
0x24 = 0x00 DSP clock cycles available per audio frame (LS bits)
0x25 = 0x7F ignore errors and disable clock auto-detect

0x28 = 0x03 I2S Format and Word Length = 32 bits
0x29 = 0x01 I2S Shift = 1

0x52 = 0x06 clock invalid flag on GPIO2
0x53 = 0x0A PLL lock flag on GPIO1

0x55 = 0x07 serial audio data output on GPIO3

Thanks again for your help,
James

0 J- over 8 years ago in reply to James Moscola

TI__Mastermind 46195 points

Hi James,

BCLK can only be sourced from SCK.

By the way, I'd recommend you to do a page swap (0x00 = 0x00) at the beginning of the Page 0 Registers section just in case.

Could you try using one of the common audio clocks and use the settings mentioned in Table 8?

Regards,

J-

0 James Moscola over 8 years ago in reply to J-

Prodigy 50 points

Thanks again for the reply. I do have the page swap in my actual configuration script, I just didn't include it in my paste job from my notes.

When you suggest using one of the common audio clocks, to which clocks are you referring? Are you suggesting I use an appropriately selected xtal+osc instead of the random 13,521,270 Hz crystal that I found in a box of old parts in my lab ;-) If so, I can certainly try that. I just need to order the parts.

James

0 J- over 8 years ago in reply to James Moscola

TI__Mastermind 46195 points

Hi James,

I refer to 11.2896 MHz or twice that.

Regards,

J-

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TAS5766M PLL won't stay locked