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TPA3251D2_slave mode

KANJI SHIBATANI
Mastermind 6205 points
Other Parts Discussed in Thread: TPA3251

Hello

My customer had chosen TPA3251D2 for next year model because TPA3251 has very low THD and High bandwidth.

Here I had 3 questions from customer below.

 

Q1   I don't kno slave mode1, slave mode2 well.

         What is the usage / purpose of the slave mode 1 and slave mode 2  ?

         Does it change the order of inter_channel_delay for  each half bridge?

         Please refer attached.

 

Q2     When IC1 is master. How do I do for IC2 and IC3 for slave?

       IC2 and IC3 should be same slave mode 1?

 

Q3     Please advise your recommended setting for  wide bandwith 40KHz +/- 1dB

          I intend to suggest 10uH/0.33uF to customer,,,,

Best Regards

TPA3251_1.TIFTPA3251_2.TIF

 

 

 

  • 0
    Mastermind 6205 points

    Hello

    Please discard  my previous questions, thank you, because local FAE had tought me.

    Additionally, please le me ask  3 questions from customer.

     

    Q1

    Filter (3R3 ohm ) placement on GVDD and VDD is different between d/s  and EVM schematic.

    Which is correct?

    Q2

    PVDD decoupling cap Data sheet 470uF +ceramic x 1, Which is recommended?

     

    Q3

    Do you recommend Direct Connection Master to Slave mode1, slave mode 2?

    Or, through resister /cap (approx 10ohm/ a few pF?)

    Please suggest me for best SNR performance

     

    TPA3251_(1).tif

     

    TPA3251_(2).tif

     

  • 0 in reply to KANJI SHIBATANI
    TI__Intellectual 1560 points

    Shibatani-san,

     

    Q2: The capacitor values shown in the datasheet are minimum requirements. There is more capacitance on the EVM to make it less critical to use a high quality power supply. The lower output impedance of the power supply vthe better. We show 4x1µF close decoupling on PVDD in both the datasheet and the EVM schematic, which is our recommendation. They should be placed as on the EVM for best effect.

    Q3: The connection of the OSC_IOM and OSC_IOP between the master and the slave devices are correct. IC1 is master, IC2 is slave1 and IC3 is slave2.

    The master IC1 should use 10kohm for nominal switching frequency (600kHz).

  • 0 in reply to sorenpoulsen
    Mastermind 6205 points

    Dear Mr Solenpoulsen-san,

    Thank you for your advice.

    Please let me confirm again about  Q3.

    I know about FREQ_ADJ pin.

    The connection between OSC_IOP(master ) to OSCIOP( slave1) should be directly connected ?

    Or should be connected through RC filter  ( a few ohm resister and cap)?

    I will ask customer to make PCB pattern with RC filter for their ES.

    The reason why customer ask is, there are no reference design schematic for master/slave mode1/slave mode2...

    Sorry to bother you again,,

    Best Regards