TAS5754M/56M Response Time for DC Offset Protection

Sadanori Kato

Other Parts Discussed in Thread: TAS5754M, TAS5760M, TAS5756M

Hi,

Could you please tell us the response time when detecting the dc offset error(DCE) although the DCE threshold is ~2.6V at the output with 24V PVDD as the following post ?

- TAS5754M Protection -
https://e2e.ti.com/support/amplifiers/audio_amplifiers/f/6/t/437068

Best regards,
Kato

over 8 years ago

0 Sadanori Kato over 8 years ago

Guru 36490 points

Hi,

We have an additional question.
Does TAS5754M/56M detect the DCE when the sine wave that overflowed as the I2S data is inputted to TAS5754M/56M ?
Could you please tell us how much period TAS5754M/56M detects DCE in if TAS5754M/56M can detect ?

Best regards,
Kato

0 Sadanori Kato over 8 years ago in reply to Sadanori Kato

Guru 36490 points

Hi,

The input signal with clipping which we are assuming is shown as below.
Could you please give us your advice about it ?

Best regards,
Kato

0 Andy Liu (BMS) over 8 years ago in reply to Sadanori Kato

TI__Guru 52115 points

Hi Kato,

Let me find the answers for you.

Andy

0 Andy Liu (BMS) over 8 years ago in reply to Sadanori Kato

TI__Guru 52115 points

Hi Kato,

What you drew doesn't have a real DC offset even though the signal is clipping. Hence, that signal will not cause a DC offset error.

Andy

0 Sadanori Kato over 8 years ago in reply to Andy Liu (BMS)

Guru 36490 points

Hi Andy-san,

Thank you for your information.
I understood that TAS5754M/56M does not detect DCE if clipping.
So, could you please give me your advice regarding the condition to detect DCE ?

Best regards,
Kato

0 Sadanori Kato over 8 years ago in reply to Sadanori Kato

Guru 36490 points

Hi Andy-san,

Could you please share the detecting condition for DCE to me since it is not mentioned in the data sheet and I need the following information such as TAS5760M ?

Best regards,
Kato

0 Andy Liu (BMS) over 8 years ago in reply to Sadanori Kato

TI__Guru 52115 points

Hi Kato,

OK. I will check whether we have similar details for the TAS5756M.

Andy

0 Andy Liu (BMS) over 8 years ago in reply to Andy Liu (BMS)

TI__Guru 52115 points

Hi Kato,

I just found a useful e2e thread which is also discussing the DC Offset Protection. You may want to take a look:

e2e.ti.com/.../1574645

Andy

0 Sadanori Kato over 8 years ago in reply to Andy Liu (BMS)

Guru 36490 points

Hi Andy-san,

Thank you for your quick response.
Unfortunately, I am not TI employee, so I cannot access the above post..
Could you please explain more information ?

Best regards,
Kato

0 Andy Liu (BMS) over 8 years ago in reply to Sadanori Kato

TI__Guru 52115 points

Hi Kato,

OK. Basically, what you see in the TAS5760 datasheet about the DC offset is also applied to the TAS5756M.

Andy

0 Sadanori Kato over 8 years ago in reply to Andy Liu (BMS)

Guru 36490 points

Hi Andy-san,

Thank you for your response.
Could you please give me your advice regarding the following questions ?

- DCE Threshold : ? V @ PVDD
- Time for Detecting the DCE : ms ?
- Fault Time Out Period : ms ?
- Fault Notice : /SPK_FAULT ---> Low ?
- Procedure for Resetting the Fault State : /SPK_MUTE ---> Low ?
- Other Details : ?

Best regards,
Kato

0 Andy Liu (BMS) over 7 years ago in reply to Sadanori Kato

TI__Guru 52115 points

Hi Kato,

See my comments below:

a) DCE Threshold : ? V @ PVDD

Andy : Refer to the table below.

b) Time for Detecting the DCE : ms ?

Andy: The outputs must remain at or above the voltage listed in the table above for more than 420 ms to trigger the DC detect.

c) Fault Time Out Period : ms ?

Andy: What does this mean? Could you explain more?

d) Fault Notice : /SPK_FAULT ---> Low ?

Andy: Refer to Page 53 in the TAS5756M datasheet for more details.

If the TAS5756M device measures a DC offset in the output voltage, the SPK_FAULT line is pulled low and the
SPK_OUTxx outputs transition to high impedance, signifying a fault. This latched error require the SPK_MUTE
line to toggle to reset the error.

e) Procedure for Resetting the Fault State : /SPK_MUTE ---> Low ?

Andy : See the comment for (d).

f) Other Details :

Andy : DCE for TAS5756M is non-latching with 1.3s retry.

0 Sadanori Kato over 7 years ago in reply to Andy Liu (BMS)

Guru 36490 points

Hi Andy-san,

Thank you for your information.

"Fault Time Out Period" for (c) means the retry period for DCE.
So, I understood that DCE is non-latching with 1.3s retry as above your comment for (f).
By the way, I am a little confused since your comment is inconsistent for (d) and (f).
I believe that it is not necessary to toggle the /SPK_MUTE line since DCE is a non-latching error and TAS5754M/56M automatically resumes the normal operation.
OTE and OCP are also same with DCE.
Is my understanding correct ?

Best regards,
Kato

0 Andy Liu (BMS) over 7 years ago in reply to Sadanori Kato

TI__Guru 52115 points

Hi Kato,

Let me double check. Basically I agree with you.

Andy

0 Sadanori Kato over 7 years ago in reply to Andy Liu (BMS)

Guru 36490 points

Hi Andy-san,

Thank you for confirming.

The data sheet for TAS5754M/56M should be updated to correct the contents since it is not necessary to toggle the /SPK_MUTE line when detecting DCE.
So, could you please revise it and give us when it is updated ?

Best regards,
Kato

0 Andy Liu (BMS) over 7 years ago in reply to Sadanori Kato

TI__Guru 52115 points

Hi Kato,

Let me talk to my colleagues and find out how soon we can update this datasheet.

Andy

0 Sadanori Kato over 7 years ago in reply to Andy Liu (BMS)

Guru 36490 points

Hi Andy-san,

Thank you for your comments.
I am looking forward to getting the latest data sheet from you.

Best regards,
Kato

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TAS5754M/56M Response Time for DC Offset Protection