TAS5754M/56M how to configure PLL for clock Master from non Audio Rate ?

Hi, Stephane,

Can you please try disabling the autodetection of MCLK in register 37 before configuring the PLL?, the device might be waiting for a valid MCLK to start normal operation as the amplifier is reporting a clock error. Also, you can read back register 95 to check if the amplifier is reporting an specific error. Another solution you might try would be to operate the device in 3-wire mode, so MCLK dependent clocks can be driven by the PLL having SCLK as the source. 

Best Regards,

  -Diego Meléndez López
   Audio Applications Engineer

Diego Meléndez said:

Can you please try disabling the autodetection of MCLK in register 37 before configuring the PLL?

I tried without success.

Diego Meléndez said:

Also, you can read back register 95 to check if the amplifier is reporting an specific error.

R94 = 0x6F and R95 = 0x11  -> all clocks errors
after some seconds
R94 = 0x7F and R95 = 0x15 -> SCLK and LRCK are missing

and indeed I have R117 = 0 -> DSP booting and DAC is powered Down

Then, after browsing the datasheet for hours, I noticed that to avoid these SCLK/LRCK missing errors we must add pull résistors.

So I did... I don't have the clocks missing errors anymore, No improvement for GPIO 2 PLL clock output.

Then I tried:

R2=0x10 Standby request
R1=0x10 Reset modules
R37 = 6 -> disable autoset and ignore SCLK/LRCK missing
R2=0 Stop standby

Still Nothing on GPIO2/MCLK...R117 = 0, DAC Powered Down. No voltage on DAC Outputs (VCOM=0) and CP/CN/CPVSS = 0 V.

Is the PLL always active or powered by the DAC module ???

How to power back the DAC module ?

I noticed that when reading back PLLFLEX registers 63 and 64 of page 253, I get 0 and not 0x11.
What is the magical value to write here ?

Diego Meléndez said:

Another solution you might try would be to operate the device in 3-wire mode, so MCLK dependent clocks can be driven by the PLL having SCLK as the source.

Not an option, my processor cannot generate SCLK and LRCK without a proper Audio clock which should be output by the TAS57574M.

Hi, Stephane,

Thanks for your reply. So, the operation mode of the amplifier would be Master mode from a Non-Audio Rate Master Clock. In this mode you should ignore Fs, SCLK and MCLK detection as these signals are not being provided to the amplifier. In order to make this, you need to write the following:

R37=0x72  -Ignore Fs, SCLK, MCLK and disable clock auto set

The configurations you have in your first post are correct, but you still need to configure the DSP, DAC, NCP and OSR dividers to configure the amplifier properly. When in this operating mode, the PLL is still being used to generate the internal clocks required by the DAC. You have currently a PLLCK of 98.30375MHz, so in order to get the DAC clocks configured, you need to set the divider registers as follows:

R27=0x01  -Divide by 2 to get 1024×Fs DSP clock (from PLLCKClock).
R28=0x0F  -Divide by 16 to get 128×Fs DAC clock (from DSP Clock).
R29=0x03  -Divide by 4 to get 32×Fs NCP clock (from DAC Clock).
R30=0x00  -Divide by 1 to get 128×Fs OSR clock (from DAC Clock).

As the clocks will be provided by the amplifier, you need to set and enable the dividers for SCLK and LRCK as follows:

R09=0x11  -SCLK and LRCK as Outputs
R32=0x07  -Divide by 8 to get 64×Fs SCLK (from 512×Fs MCLK)
R33=0x3F  -Divide by 64 to get 1×Fs LRCK (from SCLK)
R12=0x7F  -Enable SCLK and LRCK dividers

I would like to add that you may want to set register 14 to use the PLL Clock as the input of DAC clock tree.

Please try setting these values and let me know if helps. 

Best Regards,

  -Diego Meléndez López
   Audio Applications Engineer

Hi Diego,

>So, the operation mode of the amplifier would be Master mode from a Non-Audio Rate Master Clock.
>In this mode you should ignore Fs, SCLK and MCLK detection as these signals are not being provided to the amplifier.
>In order to make this, you need to write the following:
>R37=0x72 -Ignore Fs, SCLK, MCLK and disable clock auto set

Yes, I've tried already R37=0x7C, but I can try 0x76 or 0x72.

>The configurations you have in your first post are correct, but you still need to configure the DSP, DAC, NCP and OSR dividers to configure the amplifier properly.

Yes I've done this part already but didn't write it because I can't get the PLL output on GPIO2...
But maybe we need the DAC to be running first. These modules seemed independent on the datasheet, but I can't know for sure.

>When in this operating mode, the PLL is still being used to generate the internal clocks required by the DAC.

Well I've seen this as possible but this is really not explicit in the datasheet.

It just says to generate a new MCLK from PLL GPIOs and then one can only assume to refer to the normal Master mode in section 8.3.3.1 where it is asked to drive the DAC from MCLK and not the PLL....
Moreover, all diagrams show SCLK and LRCK generated by MCLK division, not DAC frequency. So again, one can only assume they need MCLK anyway.

>You have currently a PLLCK of 98.30375MHz, so in order to get the DAC clocks configured, you need to set the divider registers as follows:
>R27=0x01 -Divide by 2 to get 1024×Fs DSP clock (from PLLCKClock).

OK, 49.152 MHz

>R28=0x0F -Divide by 16 to get 128×Fs DAC clock (from DSP Clock).

that would be 6.144 MHz OK from PLL clock (and not DSP)

>R29=0x03 -Divide by 4 to get 32×Fs NCP clock (from DAC Clock).

OK, 1.536 MHz

>R30=0x00 -Divide by 1 to get 128×Fs OSR clock (from DAC Clock).

I think it should be R30=7, Divide by 8 to get 16x oversampling.

>As the clocks will be provided by the amplifier, you need to set and enable the dividers for SCLK and LRCK as follows:
>R09=0x11 -SCLK and LRCK as Outputs
>R32=0x07 -Divide by 8 to get 64×Fs SCLK (from 512×Fs MCLK)
>R33=0x3F -Divide by 64 to get 1×Fs LRCK (from SCLK)

OK

>R12=0x7F -Enable SCLK and LRCK dividers

I used R12=0x03 and maybe that's a mistake. I'll try to keep the reserved 1's as you suggest.

>I would like to add that you may want to set register 14 to use the PLL Clock as the input of DAC clock tree.

Yes I didn't try that.
Maybe I can get the DAC running from the PLL.
But I'm not sure I will get the MCLK from GPIO2, which is still required to generate SCLK and LRCK...

Hi,
I've done more tests:

1. clocking the DAC from the PLL and setting all dividers does not wake up the DAC module, and I still don't have GPIO2=desired MCLK

2. Powered OFF, I measure a big resistance between GPIO1/2 and GND/DVDDD, so I confirm there is no short.
Powered ON, I measure 25 ohms resistance between GPIO2 and GND, so I confirm it's configured as output and set to 0 by the TAS5754M.

3. So I read back the PLL configuration registers:
R8=0x20 <<< OK, GPIO 0-1 as inputs, 2 as output
R13=0x10 <<< bad, PLL Reference Clock is SCLK instead of the value I wrote 0x70 for GPIO
R18=0x00 <<< bad, reserved value instead of the value I wrote 0x02 for GPIO 1
R85=0x00 <<< bad, GPIO2 Output is OFF/LOW, instead of the value I wrote 0x10 for PLL Output/4

So everything is consistent. The TAS5754M does not take the GPIO configuration I sent.

Maybe there is a special order, or it's just consistent with the fact that we have to unlock the special "Clock Tree Flex Mode".

4. Now, it all comes down to my previous question:

What is the magical value to write in PLLFLEX registers 63 and 64 of page 253 ?

Stephane Lesage said:

What is the magical value to write in PLLFLEX registers 63 and 64 of page 253 ?

Hello, Stephane,

Thanks for your comments and feedback from the datasheet, we apologize for any confusion. Are you writing register 37 to disable the clock detection before configuring everything else in the amplifier?, I am asking because the device has a power on reset function that keeps the registers in the default state until valid clocks are provided. If you can send me the register settings you have so far I can check if there is anything else required to make the amplifier work as you need. 

Best Regards,

  -Diego Meléndez López
   Audio Applications Engineer

Hi Diego,

we apologize for any confusion.

Thanks, but there's no confusion here. Some things are just plain wrong. Please fix the TAS5754M datasheet. You can also update TAS5756M's (no register map in this one). The PCM5242 datasheet seems correct.

After getting the PLL to work with GPIOs, so I have my target MCLK = 24.576 MHz,
I tried various settings for the dividers and DAC clock source without success, amp modulating at an odd 860 kHz frequency.
I noticed that I had no more clock errors or maybe just one, so I tried removing the detection and ultimately why not keep the clock dividers auto-set active ?

MCLK is OK, DAC clock source is chosen, SCLK and LRCK dividers are fixed and active,
so actually automatic setup is working and generating nice frequencies for everybody.
My TAS5754M is finally working.

Are you writing register 37 to disable the clock detection before configuring everything else in the amplifier?

No, it seems that it's not needed after all, even if one were to setup the dividers manually.
As soon as ALL clocks are valid, the DSP, DAC, Charge pump, Amp modulator and Power stage (including GVDD=7V) will wake-up.

I am asking because the device has a power on reset function that keeps the registers in the default state until valid clocks are provided.

Yes, I've read that in the datasheet, but I don't have this problem. I always can read and write I2C registers.
Maybe my bootloader and actual firware have different settings for the Audio Serial Port,
and that triggers a simple change on SCLK/LRCK/SDIN pin which is enough to release the reset process.

Valid clocks are not needed for that, but are required to wake up from Power-Down.


In the end, here is my pseudo-code:
R0 = 0 Select page 0
R2 = 0x10 Standby request
R1 = 0x11 Reset modules + registers
R2 = 0 Stop standby

R4 = 0 Disable PLL

R0 = 253 Select page 253
R63-64 = 0x11FF Enable "Clock Tree Flex Mode" now we can use the PLL with GPIOs

R0 = 0 Select page 0
R20 = 1 Set PLL P = 2
R21 = 7 Set PLL J = 7
R22-R23 = 0x21c3 Set PLL D = 8643
R24 = 0 Set PLL R = 1
R8 = 0x20 Set GPIO1 as Input, GPIO2 as Output
R85 = 0x10 Select PLL Output/4 for GPIO2 Output
R18 = 0x02 Select GPIO1 as clock input source
R13 = 0x30 Set PLL Reference clock to GPIO (0x70 is WRONG)
R4 = 1 Enable PLL

At this point, I get the desired clock frequency output from GPIO2 to MCLK

R40 = 0 Set serial interface as 16 bits I2S
R14 = 0x10 Select PLL/4 for DAC clock source

R12 = 0x7C Reset SCLK and LRCK dividers
R9 = 0x11 Set SCLK and LRCK as Outputs
R32 = 3 Set SCLK = DAC CLK / 4
R33 = 31 Set LRCLK = SCLK / 32
R12 = 0x7F Enable SCLK and LRCK dividers

At this point all clocks are valid and the whole amp wakes up from Power Down.

Then I configure independent auto-mute for my application and it seems to work fine.

Now I can start validating SNR/THD/Max Power performance of my PCB.

Can you please validate my request for the PurePath Console so I can experiment with Hybrid Flow biquads ?

Hi, Stephane,

Thanks for your comments, any other person can reference to your findings in order to accomplish the same operating mode. We are currently working in the update/fix of the TAS5754/56 datasheet so your feedback is really appreciated. 

I have verified that your access to PurePath Console was approved last Thursday, so you can go to mySecure Software 

Best Regards,

  -Diego Meléndez López
   Audio Applications Engineer