This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TAS5754 3-wire mode question

Other Parts Discussed in Thread: TAS5754M

Hi team,

Can TAS5754 support using BCLK(No MCLK) 3-Wire mode at 96K or higher sampling rate?how to configure the device?

  • Hi, Bing,

    Yes, the TAS5754M can work in 3-wire operation mode. You need only to configure the amplifier to ignore MCLK detection since there won't be any MCLK, and set the PLL clock source as SCLK. The device will auto generate the clock coefficients. The following code showcases the required register configuration:

    # Ignore MCLK and MCLK halt detection
    w 98 25 18
    # Set SCLK as the input of the PLL
    w 98 0D 10

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • Hello Sir,

    Addition to the thread, with 3-wire I2S with no MCLK, do we need to apply BCLK before sending I2C instruction to the TAS5754 / TAS5756? I checked my sequence was functional but not sure if it is valid for volume production.

    1. Apply power supply
    2. Write HybridFlow's I2C instructions
    3. Write the following I2C instruction to sync by BCLK:

    w 98 00 01
    w 98 03 04
    w 98 00 00
    w 98 02 10 # Set the device into standby
    w 98 0D 10
    w 98 25 08
    w 98 08 10
    w 98 02 00 # Wake from standby

    4. Start sending BCLK, LRCK and Data

    Thank you and Best regards,

    Wayne Chen
    09/22/2017
  • Hello Wayne! If you are not getting any clock errors you should be OK here.

    Hello Andy! Do you see any issues with this BCLK sequence?

    Thanks, jeff