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TPA3136D2 problems running at low VCC (<8V)

David Trotter
Intellectual 730 points
Other Parts Discussed in Thread: TPA3136D2EVM

I testing the TPA3136D2EVM connected to TI 3204 codec EVM. The amplifier is PBTL mode (J13 disengaged) and connected to the CODEC through single ended connection. 

CODEC output > 1k+4.7nF filter > 1uF decoupling cap > amplifier input (RINP)

RINN is connected to ground via 1uF capacitor. (J10 engaged when using the EVM)

When the amplifier is powered with <8V I see two problems.

1) The PSRR is very poor below 8V VCC, there is noise on my VCC rail due to the boost converter working in PFM mode. As soon as you go over 7.5V (or there about) the noise disappears. 

2) Click/pop is very bad below 8V VCC. Because any change on the AVCC rail is instantly transferred to the internal AVDD/GVDD, so any voltage drop on AVCC when the PWM outputs turn on transfers over to the AVDD and GVDD rails. This creates a pop. 

3) In order to improve PSRR due to 1), I placed 50ohm + 10uF RC filter on AVCC. This helps a lot but makes the pop on turn on worse (larger voltage drop on AVCC).

I observe also that when you press the /SD button on the evm, RINP falls to 0v very quickly. Whereas RINN falls very slowly due to the probe resistance. 

When you release /SD, RINP rises instantly, RINN takes around 5ms. So it appears that the resistance to Vref for each is different. Therefore when you get any change in Vref (due to change in AVDD, from AVCC), this transfers to an offset in the inputs - causing the pop. 

---------------

 I believe this is because the internal LDO is set to output 7V so when VCC falls below this, the LDO isn't functioning. 

You can repeat my results easily using any codec and the 3136EVM board. Configure it as I have (J13 removed, J10 engaged) then try running the board at 5V then 8V - pressing the shutdown switch on and off. 

At 5v the turn on pop is much worse. Also the PSRR is much worse. 

Is the AVDD connected to GVDD somehow? Can you show me the internal structure of the power supplies please? 

I look forward to your suggestions. 

Best regards

David

  • 0
    TI__Expert 5000 points

    Hi, David 

            1) Because you use Single ended input, so you find a different rise time for RINP and RINN when release SD.

    2) In order to minimize the power turn off pop. Suggest to Shutdown amplifier first (SDZ 1--->0) then power down PVCC. 

    If without a GPIO to control SDZ, you can just use circuit like bellow (PVCC=12V), this circuit will minimize the Power on and Power off Pop/click:

    3) For the PSRR, suggest to use differential input mode.

    Yes, when PVCC/AVCC<7V, it will bypass the internal LDO. GVDD and AVDD (2*Input bias voltage) will track the AVCC.

  • 0 in reply to Peter Cao
    Intellectual 730 points

    Thanks

    That doesn't really help me though. The problem is with pop on turn on (pull standby high) with PVCC already stable. 

    The codec doesn't have differential output and adding op-amp circuit increases the noise too much. So I'm stuck with single ended input. 

    Would placing a resistor between the decoupling RINN 1uF capacitor and ground help? 

    If there any way I can filter the AVCC? I have tried using a capacitance multiplier circuit using NPN transistor. 

    Any other suggestions? 

  • 0 in reply to David Trotter
    TI__Expert 5000 points

    Hi, David

    The internal delay of 'SDZ rise to 2.0V' to 'Enable Output driver'  is 10mS.

    For single ended input mode, the charge time of  INP and INN (rise to Vbias) is different. 10ms is not enough, so you can hear the pop/click.

    No other method can solve this problem, only using differential input mode or lower the decoupling capacitor (for example 1uF to 0.47uF).

  • 0 in reply to Peter Cao
    Intellectual 730 points

    Hi Pete

    You need to read my first statement carefully. 

    This rise time isn't the problem. By 5ms both RINP and RINN have risen to the same voltage, so before the PWM outputs begin, there is no offset. I have tried reducing the RINN capacitor to 100nF and it makes no difference. 

    The problem is the drop on GVDD rail when the PWM outputs begin. The charge pump and fet switching draws current and causes a drop on the internal GVDD and AVDD rails. At 8V this is around 13mV which transfers over to the RINP immediately causing the offset and small pop. At 5V this drop is 43mV (because LDO isn't operating) so there is a much larger drop on RINP and much bigger pop.

    This is because the RINN and RINP impedances to Vref are different, so any change in Vref causes an offset. 

    So I'm not really sure how to solve this. It seems you should have designed the amplifier so RINN and RINP have a similar impedance to Vref.

    ----

    Try this yourself, stick a probe on GVDD and RINP then monitor the voltages carefully after you pull SD high. You will see both drop when the PWM outputs begin. 

  • 0 in reply to David Trotter
    Intellectual 730 points

    I've resolved this issue so I thought I would follow up on here for anyone else having a similar problem:

    I have had to add an analog switch - 74HCT1G66 and connect it's VCC to the GVDD rail and GND to AGND. This normally-open analog switch is configured to close and short the two inputs RINN and RINP together following a "high" on the enable pin. Effectively, it is an external "mute" switch. 

    This switch remains closed until 20ms after the amplifier has been turned on. This ties the inputs together so when the PWM output begins there is no offset and no pop. Once the PWM has started, the switch is released and the amplifier operates as normal. 

    An RC controlled mosfet delay circuit connected to the SHDN pin could be used if you don't have spare microcontroller pins.