TPA2028D1: Is it possible case to damage the device if we apply 0.6V(VIL_max)～1.3V(VIH_min) to EN when VDD=3.6V?

Hi Jose-san,

I appreciate for your answer however my customer wants to know the detail..

Is EN pin CMOS input?
If the answer is yes, did you say TPA2028D1 shouldn't be damaged even if intermediate level is applied to EN (CMOS input)?

Best Regards,
Yaita

Hi Jose-san,

Thank you for your support.
I had a talk with my customer and he understood what you said.
In addition he wants to know equivalent input schematic diagram of EN pin if possible.
Is it possible to send me the information?

yaita-k@clv.macnica.co.jp

Best Regards,
Yaita

Hi Jose-san,

Yes, I also believe EN input is Hi-Z. 
My customer thinks CMOS input of the device must be held at VCC or GND to prevent supply current as the following application note.
http://www.ti.com/lit/an/scba004d/scba004d.pdf
He wants to confirm if applying intermediate level to EN pin may damage the device or not in terms of current flows from VCC to GND. 

Best Regards,
Yaita / Japan disty