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TAS5717: DRC coefficient format

pascal5158
Intellectual 505 points
Part Number: TAS5717
Other Parts Discussed in Thread: TAS5711, TAS5713

Hello,

I am trying to program the DRC on the TAS5717. 

The documentation says the threshold is in 9.23 format and the other coefficients are in 3.23 format.

I do not want to use the GUI tools to produce the final configuration, but when I used the GUI tool I notice that a threshold of -48.18 dB translate to 0x00080000, a threshold of 0.13 is: 0x8200000, and a threshold of 12.04 dB is 0x20000000.

Is there a better documentation for register 0x43, 0x3e, 0x3f?

Thanks

  • 0
    TI__Guru 57800 points

    Hi, Pascal,

    The Threshold coefficients for the AGL of the TAS5717 are calculated from the linear coefficients according to the formulas in table 1 of the datasheet. the coefficients in 9.23 format are calculated the same way as 3.23 coefficients, the difference lies in the number of integer bits. There could be a small difference between the way the GUI computes the coefficients against the manually calculations. This is because the GUI could be using a different algorithm to make the calculations. You can use the attached tool as reference.

    AGL_TAS5717.xlsx

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • 0 in reply to Diego Melendez
    Intellectual 505 points

    I still cannot get the DRC to work on the TAS5717 . If you look at the data sheet (SLOS655A –NOVEMBER 2010–REVISED FEBRUARY 2011), page 4, I am trying to program the AGL at the bottom of the figure. I have programmed all path correctly to send the audio through the AGL. I am pretty sure of that.

    I also looked at the document SLOA148, June 2010, page 4 as well as the GUI tool (TAS57XX, Version 3.2 build 7).

    According to SLOA148 on page 4, it looks like I needto program DRC2 with the registers 0x3d, 0x43, 0x44, 0x45, 0x3e/0x3f. The GUI tool for the 5717 shows a panel with:

    Register 0x43: Threshold, 32 bits

    Register 0x3E: Softening Filter, 32 bits

    Register 0x3F: Attack/Release 64 bits.

    Nowhere I can see the GUI mentions 0x3d, 0x44, 0x45

    Moreover, when I generate the I2C file, I get the following for register 0x43:

    X43 00  08  00  00  00  07  FF  FF 

    So it looks like register 0x43 is a 64 bit register or perhaps it is combined with register 0x44.

    Is there any other info available that I am missing?

    Thanks!

  • 0 in reply to pascal5158
    TI__Mastermind 24835 points
    Hi Pascal,
    The register 0x3d, 0x44, 0x45 are not availabe on TAS5717. The document SLOA148 doesn't apply for TAS5717. On some devices, like TAS5711, these registers are all available. And actually DRC in TAS5717 is not as complex/powerful as TAS5711.
    Best regards,
    Shawn Zheng
  • 0 in reply to Shawn Zheng
    Intellectual 505 points

    Ok thanks, but things are not clear yet:

    The GUI tool I mentioned before seems to generate an 8 byte value for register 0x43 (DRC #2 Threshold) but the datasheet indicates that 0x43 (and 0x40) are 4 bytes registers.

    Thanks

    Pascal

  • 0 in reply to pascal5158
    TI__Mastermind 24835 points

    Hi Pascal,

    I believe it's a software issue. The register 0x43 has 4 bytes, you can access this register by I2C Memory Tools. As the following picture showing.

    Best regards,

    Shawn Zheng

  • 0 in reply to Shawn Zheng
    Intellectual 505 points
    The problem is that the registers of the DRC are not well documented in the datasheet.
    Register 0x3e is used for a low pass filter to do energy smoothing? I assume that alpha and omega should be in [0..1] but then why are they in 3.23 format. The default value for omega looks like a negative number.
    Register 0x43 is the energy level. Is there a bias? Is it a dB(FS) value in which case it should be < 0?
    Similar question for the attack and release.
  • 0 in reply to pascal5158
    TI__Mastermind 24835 points
    Hi Pascal,
    Yes, alpha and omega are in [0,1], but 3.23 format is used for them because of the internal ditial design consideration. I can't mention too much details, but your understanding is right. The default for omega is positive.
    For DRC threshod, there is a biase on it. You can refer to the document SLOA148. DRC part is the same for TAS5717.
    Release time is calculated in complement format.
    Best regarads,
    Shawn Zheng
  • 0 in reply to Shawn Zheng
    Intellectual 505 points
    Hello,

    I have tried different combinations of threshold and I am not seeing any differences. Another question I have. The GUI tools generates for register 0x46 the following:

    00 02 06 23

    But according to the datasheet some of the bits are reserved. I initialize 0x46 with:

    00 00 00 22

    because I only need DRC2.

    Cheers,

    Pascal
  • 0 in reply to pascal5158
    Intellectual 505 points
    More info:

    I am checking all the paths through the biquads of the TAS. I have also zeroed the biquad that are on a path I do not need now. This is what I have so far (refer to page 4 of the datasheet):

    L -> 0x26 -> 0x76 -> 0x31 -> 0x5c -> 0x52 -> Output => Works!

    L -> 0x26 -> 0x76 -> 0x31 -> 0x5e -> 0x52 -> Output => No audio

    If the AGL is not activated (0x46) should I get audio? Activating the AGL with 0x22 in 0x46 does not solve the problem regardless of the threshold setting. I also flipped the mixing in 0x52 to select the right path.
  • 0 in reply to pascal5158
    TI__Mastermind 24835 points
    Hi Pascal,
    Please ignore the reserved bits in the register map. If AGC is not actived in the register 0x46, AGC function is disabled, but there should be still audio output. AGC in only used to avoid hard clip in the output. Please check the master volumn in register ox07, is it big enough?
    Shawn Zheng
  • 0 in reply to Shawn Zheng
    Intellectual 505 points

    Yes the master gain is big enough because I can hear audio on the other paths. I am upgraded the software to allow me to change all the paths at runtime. First we will test all the paths without the AGC. To do that I wil also zero the biquad that are not used. That way there won't be any possible mistake. That should be easy ;-) then we will activate the AGC and see what happens.

  • 0 in reply to Shawn Zheng
    Intellectual 505 points

    I checked the paths the best I could by zeroing the biquads that are not used. I confirmed that the path:

    0x5c / 0x74 / 0x52 / Out works as expected.

    I tried:

    0x5e / 0x52 / Out => No audio without DRC activated. (I tried the 2 settings for 0x52 just to make sure)

    I also tried

    0x5e / 0x75 / 0x52 / Out => No audio

    I also checked what is being generated by the GUI tools (I set it up for 2 band drc, stereo).  The output is below. You will notice the tools says 5713, but it is targeted to 5717,

    Register 58/59 5a/5b are programmed as expected but registers 5c/5d and 5e/5f are not. Registers 31 to 39 are programmed. That means the lower path is active.

    ! I2C Configuration file for TAS5713
    X1B 00
    X46 00 02 00 03
    X1B 00
    X03 80
    X11 77
    X12 7F
    X13 77
    X14 7F
    X1C 07
    X0A 30
    X0E F1
    X50 00 00 00 10
    X25 01 02 13 45
    X70 00 80 00 00
    X71 00 00 00 00
    X74 00 80 00 00
    X75 00 00 00 00
    X46 00 02 06 23
    X05 40
    X56 00 40 00 00
    X57 00 02 00 00
    X07 03 FF
    X40 0D 48 00 00 09 09 FF FF
    X07 00 00
    X07 03 FF
    X3B 00 20 00 00 00 40 00 00
    X07 00 00
    X07 03 FF
    X3C 00 00 10 00 FF FF FF FD
    X07 00 00
    X07 03 FF
    X43 0D 48 00 00 04 38 87 4E
    X07 00 00
    X07 03 FF
    X3E 00 00 10 00 00 7F FF 00
    X07 00 00
    X07 03 FF
    X3F 00 00 10 00 FF FF FF FD
    X07 00 00
    X51 00 80 00 00 00 00 00 00
    X52 00 80 00 00 00 00 00 00
    X58 00 7C 7E 7B 0F 07 03 0A 00 7C 7E 7B 00 F8 E4 62 0F 86 EA 75
    X59 00 7C 7E 7B 0F 07 03 0A 00 7C 7E 7B 00 F8 E4 62 0F 86 EA 75
    X5A 00 00 0C 4A 00 00 18 94 00 00 0C 4A 00 F8 E4 62 0F 86 EA 75
    X5B 00 00 0C 4A 00 00 18 94 00 00 0C 4A 00 F8 E4 62 0F 86 EA 75
    X26 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    X30 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    X73 00 80 00 00
    X72 00 00 00 00
    X76 00 00 00 00
    X77 00 80 00 00
    X4F 00 00 00 06
    X6A 00 0C CC CC 00 73 33 34
    X27 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    X28 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    X29 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    X2A 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    X2B 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    X2C 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    X2D 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    X2E 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    X2F 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    X31 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    X32 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    X33 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    X34 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    X35 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    X36 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    X37 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    X38 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    X39 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    X07 03 FF

  • 0 in reply to Shawn Zheng
    Intellectual 505 points
    I checked the paths the best I could by zeroing the biquads that are not used. I confirmed that the path:

    0x5c / 0x74 / 0x52 / Out works as expected.

    I tried:

    0x5e / 0x52 / Out => No audio without DRC activated. (I tried the 2 settings for 0x52 just to make sure)

    I also tried

    0x5e / 0x75 / 0x52 / Out => No audio

    I also checked what is being generated by the GUI tools (I set it up for 2 band drc, stereo). The output is below. You will notice the tools says 5713, but it is targeted to 5717,

    Register 58/59 5a/5b are programmed as expected but registers 5c/5d and 5e/5f are not. Registers 31 to 39 are programmed. That means the lower path is active.

    Is there anyway with the GUI tool to get 5c/5d and 5e/5f programmed?

    ! I2C Configuration file for TAS5713
    X1B 00
    X46 00 02 00 03
    X1B 00
    X03 80
    X11 77
    X12 7F
    X13 77
    X14 7F
    X1C 07
    X0A 30
    X0E F1
    X50 00 00 00 10
    X25 01 02 13 45
    X70 00 80 00 00
    X71 00 00 00 00
    X74 00 80 00 00
    X75 00 00 00 00
    X46 00 02 06 23
    X05 40
    X56 00 40 00 00
    X57 00 02 00 00
    X07 03 FF
    X40 0D 48 00 00 09 09 FF FF
    X07 00 00
    X07 03 FF
    X3B 00 20 00 00 00 40 00 00
    X07 00 00
    X07 03 FF
    X3C 00 00 10 00 FF FF FF FD
    X07 00 00
    X07 03 FF
    X43 0D 48 00 00 04 38 87 4E
    X07 00 00
    X07 03 FF
    X3E 00 00 10 00 00 7F FF 00
    X07 00 00
    X07 03 FF
    X3F 00 00 10 00 FF FF FF FD
    X07 00 00
    X51 00 80 00 00 00 00 00 00
    X52 00 80 00 00 00 00 00 00
    X58 00 7C 7E 7B 0F 07 03 0A 00 7C 7E 7B 00 F8 E4 62 0F 86 EA 75
    X59 00 7C 7E 7B 0F 07 03 0A 00 7C 7E 7B 00 F8 E4 62 0F 86 EA 75
    X5A 00 00 0C 4A 00 00 18 94 00 00 0C 4A 00 F8 E4 62 0F 86 EA 75
    X5B 00 00 0C 4A 00 00 18 94 00 00 0C 4A 00 F8 E4 62 0F 86 EA 75
    X26 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    X30 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    X73 00 80 00 00
    X72 00 00 00 00
    X76 00 00 00 00
    X77 00 80 00 00
    X4F 00 00 00 06
    X6A 00 0C CC CC 00 73 33 34
    X27 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    X28 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    X29 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    X2A 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    X2B 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    X2C 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    X2D 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    X2E 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    X2F 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    X31 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    X32 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    X33 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    X34 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    X35 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    X36 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    X37 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    X38 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    X39 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    X07 03 FF
  • 0 in reply to pascal5158
    TI__Mastermind 24835 points
    Hi Pascal,
    We have a GUI bug which looks like the cause of your problem. GUI is not writing the right channel BQ coefficients for the crossover of the 2-band DRC. The workaround would be to copy the coefficients from registers 0x58 to 0x5B and use them to manually program registers 0x5C to 0x5F as follows:
    0x58 → 0x5C
    0x59 → 0x5D
    0x5A → 0x5E
    0x5B → 0x5F
    If it still doesn't work, please send me email. I will send you a setup and we will talk off-line. My email is shawn-zheng@ti.com.

    Best regarts,
    Shawn Zheng