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TAS5760L: Suggestion I2S DAC+amplifier

Part Number: TAS5760L

Hi,

I want some help choosing a DAC+amplifier (3 W - 15 W mono or stereo) with I2S for my project.
The ucontroller can generate a stable MCK of maximum 4 MHz, here are some of the variations of clocks it supports:

The ucontroller is also compatible with I2C and SPI if there is any need for configuration, but I prefer I2C.

I have previously tried the TAS5760L, but I always got a clock error with the clocks set to 64*fs(fs=45454.5Hz) for MCLK and 32*fs for SCK/BCK. The start up procedure was also followed as mentioned in the datasheet.

Hope you can help!

-Erblin

  • Hi Erblin,

    Sorry for the delay in getting back to you on this. This question sounds like the same problem we were discussing here e2e.ti.com/.../584561

    Were you able to get the answers you were looking for in terms of timing tolerances in the i2s spec I linked to? I found some additional information in the TAS5766 datasheet (section 8.4.2.2 System Clock Input) where it states a ±4% tolerance on the clocks. While this is not the 5760 chip you are using the tolerances may be similar. Have you had any luck with the frequencies in your table with low LCLK % error?

    Regards,

    Alex
  • Hi,

    About the I2S timing requirements, it is not possible for me to measure those parameters because my oscilloscope is not to precise. But I think the the ucontroller is featured to have and meet the I2S bus requirement, here is the electrical specification of the I2S bus on my ucontroller:

    I have also tried generating different LRCK's, but I have had no luck with this as it show the same clock error on the status register.

    -Erblin

  • Hi Erblin,

    I have checked with our design team about the allowable variation in the i2s clocks. I will let you now what I hear back from them. Is it possible for you to use an i2s source different from the uC to eliminate any potential problems with the board and see if you still get a clock error?

    Regards,

    Alex

  • Hi,

    Unfortunately I don't have other ucontrollers that supports I2S.
    But I have tested my current ucontroller with another DAC which only uses 3-wire I2S(LRCK, BCK, SDIN), this works perfectly fine with almost all supported frequencies.

    -Erblin

  • Hi Erblin,

    Thanks for the patience, I know there has been a lot of back and forth on this. In the table you provided with the supported I2S frequencies, I see your uC can generate MCLK with 32, 64, and 256 multiple of Fs only.

    I also noticed that you said the max mclk supported by your device is 4MHz. However, it looks like all the 256*fs rows have higher than 4MHz clocks (perhaps with the exception of fs = 16000Hz in which the error puts you right at 4MHz). Are you unable to generate the lrclk = 32kHz, mclk = 8 MHz and lrclk = 44.1kHz, mclk = 10.666 MHz rows in your table?

    The reason I ask is that our device does not support 32*fs for mclk or 16khz for lrclk. This leaves only 4 possible combinations from the ones you provided (two at 64*fs and 2 are 256*fs). I am still working with our design team on understanding the limitations of 64*fs for your application and will follow up with you on that. However, I am interested in whether you can test this with the 8MHz or 10.666MHz settings (the two settings that use 265*fs). I understand this may not work since you did mention you couldn't go above 4MHz. If so are there any other settings you can use with your uC to get lrclk in a supported range for the TAS5760 (32,44.1,48, etc) and an mclk multiple of 128, 192, or 256 times lrclk?

    Regards,

    Alex
  • Hi Alex,

    Yes, I was able to generate all the clocks that were listed on the table, but the one with lrck=44.1 KHz (and MCLK = 10.667 MHz) is not within specification as it deviates -5.5 % (41667,67 Hz) from the actual sample rate.

    For the supported MCLK rates it was just that the specifications listed on the I2S timing table were tested using MCLK's up to 4 MHz. I have used many variations of the clocks for testing, some with even 512*LRCK(512*31250) as MCLK. Below I post a picture with clocks I have used to test (marked yellow).



    -Erblin

  • Hi Erblin,

    I see. It is strange that none of these configurations work. If you would like to share your design files I would be happy to take a look at the layout/schematic of the board you are using in this test. Also have you tried switching out the TAS5760 IC (soldering a new 5760 IC replacement on to the board)?

    Regards,

    Alex

  • Hi Alex,

    Below I have posted the PCB design files.

    And no I have not tried to switch the IC, but I have used two different  PCB's , one in hardware control and the other software control

    TAS5760L Krets(2).pdf

    TAS5760L Krets.pdf

    TAS5760L PCB.pdf

    -Erblin

  • Hi,

    Are you using jumper wires to connect this board to the uC? I have seen that using jumper wires can cause problems if the length is too long so if this is the case I would try making them as short as possible.

    Also what is the max sample rate of your logic analyzer? Can you get more resolution by using fewer channels? It would be nice to see the waveform on mclk at the device.

    I was wondering if it could be a manufacturing problem, which is why I suggested switching ICs, but if you tried two boards this is probably okay.

    If you let me know what uC you are using I can check that as well.

    Regards,

    Alex

  • Hi,

    Yes, I have been using jumper cables(about 10 cm long) to test the DAC. I will be making another PCB with header pins connected directly to ucontroller, I have seen that pad capacitance is an important parameter for the GPIO`s.

    The maximum sample rate is 50 MHz, and yes I can disable some of the channels.

    The ucontroller I am using is the nRF52832 from Nordic Semiconductors.

    -Erblin

  • Erblin,

    50MHz should be good enough to measure MCLK. It might be worth checking the waveforms at the device. Sounds good. Keep me posted. If I see anything in the uC datasheet that stands out I will let you know.

    Regards,

    Alex
  • Hi Erblin,

    There is a chance that the jumper wires are causing an issue since the i2s DAC you were able to get working had no MCLK and this highest frequency signal would be the most effected by parasitic effects.

    Regards,

    Alex