TAS5754M: I2S clock settings

Hi Jesse-san,

Please refer to the following post and try the script.

https://e2e.ti.com/support/amplifiers/audio_amplifiers/f/6/p/516127/1881021#1881021

Best regards,
Kato

Thanks for the reply Kato. I've tried that already:

 writereg(0x00, 0x00);

 writereg(0x02, 0x10);

 writereg(0x25, 0x18);

 writereg(0x0D, 0x10);

 writereg(0x02, 0x00);

Every command ACK's, but music sounds terrible (cracking noise). Here are some scope pictures of my I2S signal:

SCLK

LRCK/FS

LRCK/SDIN/SCLK combined

The BT module may very well be the cause, but the signal looks fine (although a bit noisy). So for now I suspect the TAS clocks.

Hi Jesse-san,

Do you hear the noise sound evne if applying the I2S signal to your board by using AP instead of BT module ?
In addition, please try to apply the external I2S signal to TAS5754MDCAEVM via BT module if you have the TAS5754MDCAEVM.

Best regards,
Kato

Hello! I have also looped in Roy to help out here. Thanks, Jeff

Thanks Jeff, all support is appreciated.

If it helps, this is the timing diagram of the BT module:

Kato, what is 'AP'? I tried to apply I2S to the EVM, but no sound.

I apply I2S to the PSIA header, set input to PSIA in PPC2,  disable SCLK and MCLK halt detection and set SCLK as the input of the PLL

Applying I2S to my custom PCB gives some noise, but it's barely recognizable as music.

Hi Jesse,

Have you tried to configure PLL manually? If not, please follow the instructions from P.39 to P.44 in TAS5754M datasheet to set it.

Please be reminded that you'll need to disable clock autoset in register 0x25.

In Table 6, you'll be able to find the combination of your clock frequencies and the corresponding PLL parameters.

Registers that need to be configured include 0x14, 0x15, 0x16, 0x17, 0x18, 0x1B, 0x1C, 0x1D, 0x1E, 0x22, 0x23 and 0x24.

Please let me know if you have any question. Thank you!

Best regards,

-Roy Hsu

Texas Instruments

Hi Jesse-san,

The AP which I mentioned above is an abbreviation for "Auido Precision".
I understood that a sound doesn't come out if applying I2S signal to TAS5754MDCAEVM via BT module which you used.
So, does TAS5754M work normally if using TAS5754MDCAEVM with 4-wire PCM ?
If yes, as Roy-san said, please try to configure the internal PLL manually if using TAS5754M with 3-wire PCM.
However, I have confirmed that TAS5754MDCAEVM works normally with 3-wire PCM in the past as below.

https://e2e.ti.com/support/amplifiers/audio_amplifiers/f/6/t/462771

Best regards,
Kato

Are these the settings I need? Just to be clear, this is my input:

-LRCK/FS=44.1Khz

-SCLK=2.82Mhz

So I would need to adjust the following registers (register, value)

(0x14, 0) set P-factor to 1

(0x15, 16) set J-factor to 16

(0x16, 0) set D factor to 0000

(0x17, 0) set D factor to 0000 //not too sure about this one

(0x18, 1) set R factor to 2

(0x1B, 1) set DSP clock divider to 2 (based on PLL VCO divided by DSP CLK, is this correct?)

(0x1C, 15) set DAC clock divider (NDAC) to 16

(0x1D, 3) set NCP clock divider (NCP) to 4

(0x1E, 7) set OSR clock divider (DOSR)

(0x22, 0) set 8x interpolation and single speed Fs

(0x23, 0) //no idea which value to use, please explain

(0x24, 1) //no idea which value to use, please explain

(0x25, B1111111) disable clock auto set and ignore all errors

Kato, I don't have any AP gear.

EVM works with 4-wire (so from USB), but I don't get any sound after modifying the registers and selecting PSIA input (BT module input) 

Thanks for helping

Hi Jesse,

Registers 0x23 and 0x24 specify the number of DSP clock cycles available in one audio frame, that is DSP CLK divided by LRCLK frequency.

In your case, that's 45.1584 MHz/44.1 kHz = 1024. Therefore, the correct settings for these two registers would be (0x23,4) and (0x24,0).

Also, you don't need to disable every clock detection. A practical setting would be (0x25, B00011010).

The rest of the register settings look fine for me. Please let me know if there's any question.

Best regards,
-Roy Hsu
Texas Instruments

Hi Jesse-san,

Thank you for your reply.
Please try to verify it again according to Roy-san advice.

Best regards,
Kato

Hello Jesse! Did this address you question? Thanks, Jeff

No, it still doesn't work. I've heard from someone else who got his BT module to work properly that it puts out TDM (instead of the advertised I2S).

I've set P0-R40 to B010010 but that doesn't help. Are there other register that need to be modified to use it with TDM input?

Hi Jesse,

Register 41 also needs to be set according to the data offset of each device.

How many data channels do you have from the BT module?

Also, please make sure that you have the PLL settings match with the TDM clocks.

Thank you.

Best regards,

-Roy Hsu

Texas Instruments

Ok, this is interesting. I accidently toggled p0-r9 instead of p0-r19 and now it sounds crystal clear on lower volume. I wrote:

writereg(9, B00010001);
delay(50);
writereg(9, B00010000);

I don't really understand why this changes the sound. I toggled the last bit, which toggles LRCK/FS to output (I2S master).