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TAS5760M: Power-on Sequence for PBTL configuration

Sadanori Kato
Guru 36490 points
Part Number: TAS5760M
Other Parts Discussed in Thread: TAS5760XXEVM

Hi,

There is the point that doesn't obey the power-on sequence which is mentioned for PBTL configuration in TAS5760M data sheet as below.
Do you have any concerns when /SPK_SD pin is de-asserted to "high" for several seconds if the external components are set in PBTL configuration before setting the registers via I2C bus after the power-on ?
At this time, I2C clocks have already been applied to TAS5760M but the zero data is input to TAS5760M as the audio source.

Best regards,
Kato

  • 0
    Guru 15950 points

    Hello Kato San,

    I believe that it will damage the TAS5760 device with your power up sequence:

    The TAS5760's output configuration is BTL mode in default. With your power up sequence, the SPD_SD# goes high before switching it to PBTL mode by I2C. I assumed your description, "At this time, I2C clocks have already been applied to TAS5760M but the zero data is input to TAS5760M as the audio source", should be "I2S clocks have already been applied...". In this condition, the TAS5760's CH-A and CH-B will send their own Class-D PWM signal, however, with PBTL's hardware connection, the OUT+ and OUT-'s PWM will short together and damage this device.


     Please do not hesitate to inform me if you have any suggestion.

    Thank you and Best regards,

    Wayne Chen
    11/14/2017

  • 0 in reply to Wayne Chen (ex FAE)
    Guru 36490 points

    Hi Wayne-san,

    Thank you for your quick response.

    Please see the attached the power-on sequence and give me your advice again.

    Is my understanding correct that TAS5760M may detect the OCE event since SPK_OUTA+(SPK_OUTB+) is connected to SPK_OUTA-(SPK_OUTB-) after the LC Filter in PBTL configuration like TAS5760XXEVM schematic ?

    Best regards,
    Kato

  • 0 in reply to Sadanori Kato
    Guru 15950 points
    Hello Kato San,

    Thank yo for reminding me. There is over current protection mechanism with the TAS5760 which can protect this device from damage in your PBTL configuration, While I would suggest to assert SPK_SD# to high after PBTL configuration to avoid OCE be triggered.

    Thank you and Best regards,

    Wayne Chen
    11/14/2017
  • 0 in reply to Wayne Chen (ex FAE)
    Guru 36490 points

    Hi Wayne-san,

    Thank you for your prompt reply.
    I understood and will contact you if I get additional questions from our customer.

    Best regards,
    Kato