DIX4192: Problem in reading Status Register of DIR

Hi Arup,

Can you please share waveforms for CS, CDIN, CDOUT and CCLK signals during your SPI read/write? 

I am assuming you are following the host interface operation for SPI mode as defined in the DS (Section 9.4.1). The waveforms will help clarify the disconnect. Thanks.

Best regards,
Ravi

I am following exactly what is written in 9.4.1 of DS. The most significant bit set Hi before writing the respective register. It may be difficult for me to send you the waveform. Rather , I request you to send me a sample code  for reading the status registers.

Regards. 

Arup

Please find attached wave forms for CCLK and SS of SPI as obtained from Oscilloscope.  I have a further observation that the interrupts are generated( Through INT line of DIX4192) only if  status resisters of DIR is read through SPI read command. I find this is an abnormal operation as  INT should be generated depending on any unmasked error condition present in the DIR input stream( I have configured 0x16 register with 0xf4). Please clarify in details why this is happening.

Regards.

How long it will take to get my issues resolved ? Is anybody from TI can answer my queries ?  

Hi Arup,

I was out-of-office for the holidays and most of our team was also out and hence the delay. 

I'll look at the additional details you have provided and will have an update. Thanks.

Best regards,
Ravi

It is already more than a month I raised my issues but it remained unsolved till date . I do not know whether it is better to switch over to other make ? This is my first experience with TI. I have been a regular user of embedded solutions from FreeScale, Cypress, Cirrus Logic, NXP, Silicon Lab, Xilinx  etc . Never felt so helpless before !  TI support surprises me for the first time. Can I expect a concluding reply now ?

Regards.