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TPA3116D2: PBTL / mono mode layout suggestions for passing FCC part 15 B testing

Part Number: TPA3116D2

Hello,

I have a TPA3116D2 design with PBTL mode driving a 4 ohm load. I cannot find any examples of how to layout the PCB for this design (using 2 inductors). Specifically I need the design to have good EMC and pass FCC part 15 B. The EVAL board claims to do this but they give no info as to the conditions (PVCC, power output level etc,) and I assume it was not in PBTL mode. Should the routing of the outputs each go to their own snubbers (as on the EVAL board) before bridging together into the inductor? Any advice is appreciated.

Thanks,

Greg

  • Hi Greg,
    TPA3116D2 can pass CISPR B EMI test with enough margin. Usually we did this test with 2*1W/4 W/10W output power and high to 24V power supply in the measurement. Please add the snubbers on each output pins to minize the ringing on the PWM output. You could find more info in this document: www.ti.com/.../slva255.pdf
    For the PCB layout design guide, please refer to the section 10.2 in the datasheet. It's a BTL mode example, but most of the descriptions also apply to PBTL mode. Make sure the return current loop from the LC fitler to the device GND pins is as tight as possible. We can help to review your PCB dsign if you need it.
    Best regards,
    Shawn Zheng
  • Hi Greg,

    datasheet of TPA3116D2 and datasheet of EVM contain very useful information reffering to your question. Yes, do it exactly as the EVM recommends it: Connect the two lines directly at the output of EVM board, or, by other words, behind the individual LC-filters and Zobel networks.

    Kai