Part Number: INA240-Q1
When Vs=0V,IB(Input Bias Current) is indicated on Fig.15 of DataSheet
In order to suppress this current, we want to suppress the current by adding an FET between GNGPIN and GRANDPLANE.
Is it possible to suppress the IB in this way?
Also is there any influence on the electric characteristics when FET is put in?
Best Regards Koji Hayashi
Mitch M, TI Applications Support
In reply to Mitch M:
Thak you for four support.
When adding FET, does REFPIN connect to GNDPLANE?
Or is it connected to GNDPIN?
Written on P.12 of datasheet.
NOTE Do not connect the REF1 pin or the REF2 pin to any voltage source lower than GND or higher than VS.
Best RegardsKoji Hayashi
In reply to Koji Hayashi:
Either would be fine to do, but there are some trade-offs. For example, if you connect the REFPIN to GNDPLANE then you will still have a path to GND when your FET is open, although this would be very high resistance and would probably only leak on the order of micro amps. However, with this setup you would have a more accurate measurement than connecting the REFPIN to GNDPIN because when connecting to GNDPIN whatever voltage offset your FET introduces will show in your measurement. On the other hand, connecting to GNDPIN allows you to completely remove GND from your device when the FET is open, avoiding the small current leak. So it really depends on what is more important to your design.
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