• Resolved

LMP92064: Number of effective (noise free) bits

Part Number: LMP92064


I'm currently using the LMP92064 on a custom board and, for comparison, on the LMP92064 EVM board. The EVM board and the custom board have the same behavior and a very similar circuit design.

After analyzing the effective resolution in bits, I found that the lowest 4 bits on both ADCs, current path and voltage path, are very noisy. I can average the values, which works quite good, but only 8 bits of effective resolution for a 12 bit ADC seems like a little bit too much noise. I was expecting about 2 bits of noise for a 12bit ADC.

 Is that kind of noise expected? Do I have to split the V_digital and V_analog inputs to get a more stable reading? Or is that the trade off for the 125kSps?

Thank you very much in advance

and Happy Holidays

Lukas Eckert


  • Hello Lukas,

    As long as the VDIG and VDD power supplies are bypassed with capacitors close to the VDIG and VDD pins, then not splitting these supplies should not be a problem. Additionally, the REFC pin should also definitely have a bypass capacitor as well, but this should all come standard with the EVM board from what I can see.

    According to your data, you are seeing 300uVpp noise for your shunt voltage measurements and 7.5mVpp noise for your bus voltage measurements. 2^4 - 1 =15 counts * 20uV = 300uV and 15 counts*500uV = 7.5mV, where 20uV is the current ADC LSB and 7.5mV is the voltage ADC LSB.

    Have you measured the noise on you bus voltage rail or current noise? What is your common mode voltage, current value, and shunt resistor value? Is that all at room temperature? Is there any chance you could place your board inside a Faraday cage (metal box) and check the noise again? I think these are values you could expect overall. I'm not sure if the internal ADCs of LMP92064 are SAR or delta-sigma, but a 12-bit ADC is most likely a SAR, which means there is no internal averaging.

    If you compare the LMP92064 with the very similar INA226 you can see how this internal averaging could make sense. For the INA226, the interal ADC is a 500kHz, 16-bit, delta-sigma ADC in which the conversion times (or averaging) can be adjusted. At its lowest conversion time of 140us, which is approximately 70 samples averaged, the output noise is seen to be 25uVpp. See figure below from the datasheet.

    Compare this to no averaging and an 8x higher LSB with the LMP92064, in which you observe 300uVpp noise and this does not seem unreasonable.

    Best Regard,

    Peter Iliya

    Current Sense Applications

  • In reply to Peter Iliya:

    Hello Peter,
    thank you for your quick answer and for the explanation/comparison to the INA226. It makes much more sense now.

    The sensor is for low side measurements, so the common mode voltage is near 0V.

    I also checked the noise on the 5V bus voltage rail and found some periodic (2.5us) 300mVpp noise from the step down converter used to power the sensor and the load to measure. This is also not ideal, but the simultaneous voltage and current measurements of the LMP92064 should minimize this effect.

    I will use a software side median filter to filter out the noise.

    Thank you again
    Lukas Eckert