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INA226 - I2C Address selection mechanism

Guru 19775 points
Other Parts Discussed in Thread: INA226

Hi Team,

Could you please tell me the mechanism, how INA226 recognizes the serial bus address ?

In the datasheet, Table 7 shows that slave address is set by A1/A0 pins connected to Vs+, GND, SDA or SCL. 
What and when does the device monitor the A1/A0 pin voltage when it is connected to SDA or SCL ?

Best Regards,
Kawai

  • Hello Kawai,

    Thank you for your question. The state of pins A0 and A1 is sampled on every bus communication and should be set before any

    activity on the interface occurs. Hope this helps.

     

     

  • Hello Rabab-san,

    Thanks for the information. I believe the A0 and A1 is sampling the SDA/SCL voltage at Start Bit (SCL=High, SDA= transition High to Low).

    Customer were worrying that slave address may be miss programmed depending on the power sequence, however, I believe there would be no problem as long as Vs and I2C pull up voltage is stable.

    Would there anything you have to be careful when selecting slave address or using this device ?

    Best Regards,
    Kawai

  • Hello Rabab-san,

    Our customer requests for further detail information for the slave address selection mechanism. They want to make sure that there would be no miss selection of the slave address.

    I read the datasheet and it also said that the device samples A0 and A1 on every bus communication.
    Does the device monitor before and after the high to low transition of SDA/SCL at the I2C start condition ?

    If so, what would be the minimum time from SCL start condition high to low transition to the next SCL rising edge ? I believe that as long as the signal is following the I2C standard, there would be no problem ?

    We would be grateful for your help.

    Best Regards,
    Kawai
  • Hello Kawai-san,

    It would be best to have a stable Address before the start condition and maintain it until the address is acknowledged.

     

  • Hello Rabab-san,

    Thanks for the prompt reply.

    How can you know if the device has stable address or not before starting I2C communication ?

    We would appreciate it if you could explain the mechanism in detail how the device recognizes the address information at every I2C communication, by pulling up A0 and A1 pins to VDD or SDA or SCL pin. If the pull up voltage of I2C line is the same VDD, the voltage at VDD, SDA and SCL pins would be the same level before starting I2C communication. How does the device detect the differentiation between each pins ?

    Best Regards,
    Kawai
  • Kawai,

    This is an unusual question. Why is the customer concerned with the address bit response time? Generally, these bits are set on the PCB with a copper trace to the appropriate pin or level. If you have multiple devices on the same bus, then they would each have different hardware addresses. It wouldn't make sense to change them because you would still have to send data to an address, whatever it is, so it might as well be stable. What is the application?

    We have not done formal testing and characterization of the timing specs of the address pins like we have with SCL and SDA that I am aware of. I assume the customer wants to know how fast they can set the address and then send data to the device, is that true?
  • Hello Jason-san,

    Thanks for your reply.
    Our customer is considering to use this device for their ASIC evaluation and reference board.

    What they are concerning most is that if there are any limitation for their I2C host as they do not know how the device set using SDA and SCL pins. We appreciate it if you could disclose us how the device distinguishes the pin setting (A1=GND, A0=VS+), (A1=GND, A0=SDA) and (A1=GND, A0=SCL).

    Thanks and Best Regards,
    Kawai
  • Kawai,

    The answer is that the INA226 compares the inputs of A0 and A1 with SDA and SCL to see if they are shorted together, and then set the I2C address internally based on the results of that comparison. There are no limits on the host. We really can't provide more detail into the I/O cell and logic design.

    I hope this is satisfactory.
    Jason
  • Hello Jason-san,

    Thanks for your continuous support. I understood that the detail mechanism cannot be disclosed and no limitation on the host side.
    I believe there would be no trouble as long as A1/A0 pins are tied correctly.

    Thanks and Best Regards,
    Kawai