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TL082 capacitor drive capability

Other Parts Discussed in Thread: TL082, TL081

Hi,

I have a circuit where I use a TL082 amplifier to drive an RC filter. At this moment, the filter is a 100n capacitor C9 with a 10R resistor R14. This may be quite a high output capacitance for the opamp. Could it cause instability in the opamp?

I have looked at the datasheet but did not find a maximum allowed output capacitance. How do I calculate which R*C combination is the minimum allowed number?

By the way, the circuit is a peak detector circuit. It is used to detect the peak of a PWM square wave signal. Supply is +/-14V.

  • First your peak detector will require high currents during transients.  If output of TL081 is near 13V then peak current out is 13V/10 ohm or 1.3A thorugh the 100nF capacitor.  Max R-C for load on TL081 for stability would be 100 ohm and 10nF but this is still too low of resistor value for peak currents out of TL081 during transients.  Look at maximum output swing versus load resistance and raise vlaue of 10 ohm resistors to meet your desired large signal swing.  Lower cap value to keep the same R-C time constant.  Run SPICE simulations and look at output peak currents from TL081.  Let us know if more questions. 

     

  • Folkert,

    The TL081 has an output impedance (resistance) that is about 200 ohms. Therefore peak output current will not be excessively high. Typical unloaded bandwidth is 3MHz. The zero frequency of 10 ohms and 100nF is 160kHz at 14 ohms. The estimated bandwidth is 3MHZ * 14 / (200 +14) = 196kHz. This simple math shows that 10 ohms may or may not be large enough. I recommend 20 ohms.

  • Output impedance spec of 200 ohms on TL081 is a small signal AC output impedance spec. For closed loop. large signal the open loop output impedance is reduced by loop gain (difference between open loop Aol and closed loop gain). This application will slam back and forth into output current limit depending upon the input frequency range. 

  • Tim,

    The diodes only allow charging the cap quickly. So the peak positive current is limited by internal resistors, the long bleed time prevents frequent peaks. Shorts are allowed if die temperature is not exceeded. I do not have the small AC impedance value at hand. I was speaking about the physical internal resistors in the data sheet.

    .

     

  • Hi,

    Thank you for your answers, this gives me more insight into the limits of this opamp and circuit.

    If I look at the maximum peak output voltage vs load resistance graph (datasheet SLOS081G), then it seems that the output impedance is indeed around 200Ohm (the line crosses 1/2*15V=7.5V at 250Ohm). If the opamp indeed has 200Ohm output impedance built into the circuit then this limits the peak current and thus protects the circuit against excessive currents. Then the only question would be whether the opamp is damaged at worst-case peak current.

    When I simulate the circuit with the spice model from TI, I can see the output peak current is about 26mA. This is quite low, probably because I do not need to drive the capacitor all the way from -15V to 15V (but from 0V to 3V). The current seems harmless to me.

    Do I need to worry about instabilitiy of the circuit? As Ron points out, the diode limits the high currents to charging only, but this is just what makes this circuit more dificult to analyze from an AC stability/instability perspective.

  • Folkert,

    Test how the OPAMP output responds to a step in input voltage. The response will show if the stability is good or poor.

     

  • what is output driving capability in opamp  when it is driving  purely capacitive load?

  • Waseem,

    For unity gain 200pF is maximum.
  • thanx  for ur reply... i have designed unbuffered 2 stage op-amp.  for the slew rate    10v/u S  for the 10pf cap load....now i want max CL and IL(max)


    now as u said the max CL configured as unity gain is 200pf,,,how it is ?????can u please give detain on this.

    in my design i checked max CL, by varying  it ,but  for the 15pF only my slew rate has changed as compared to what is given in the spec.

    for calculating max CL,which analysis should i do,AC or tran?


    i am new to the analog design,correct me if i am wrong anywhere/

  • 200pF is for loop stability not for any slew rate concern. A transient test on the output is good to check stability by observing the device's corrective response.
  • Sir   r u   trying to tell is op-amp should not oscillate while driving cap of this much load configured as voltage follower.

    am i right??

  • Waseem,

    Yes that is correct.
  • i have 1 doubt....
    for instabiliy,regardless of whatever the input whether it will oscillate or
    does it requires the frequency in which gain and phase margin will meet(example ... In UGB mode may be at one of the frequency where phase is 0 or 360 deg it will oscillate)..please clarify.....


    for checking this in simulation,what are the analysis have to be done and inputs that have to be given....
  • Waseem,

    The circuit has a lot of components so the easiest way to check stability is to look at the op-amp pin wave forms and check for oscillation or ringing.

  •  i have done simulation configured as UGB,i provided step input at non inverting side, it is not showing any continuous oscillations for any of the cap value...(i checked even till 100u F)
     but ringing in the output side is happening...
     even small ringing should be treated as unstable or what? please clarify....
     should i need to consider overshoot?

  • Wassem,

    See page 3 for cross checking ringing vs phase margin.

  • hi ronald

    the link is not opening.

    regard
    waseem
  • http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=SLVA381&fileType=pdf&keyMatch=slva381&tisearch=Search-EN
    How about this one?

    Otherwise go to TI.com and search for SLVA381.
  • Ronald

              thank u so much:)

    regards

    waseem

  • hi ronald

    what is the relation between rise time and unity gain bandwidth?
  • Vishwas,

    Sorry for the delay. Rise time is related to slew rate which is usually set by error amp output current and main compensation capacitance. SR = I/C.
    bandwidth is set by open loop gain and compensation cutoff frequency. So slew rate and bandwidth are not closely related although both are based on compensation capacitance.
  • hi ronald

    this what   i got from net..


      for single dominant pole compensation,,rise time is given by tr=0.35/BW                   BW--Bandwidth

    So unity gain bandwidth is given by UGB=ACL*0.35/tr         ACL-closed loop gain...

    is it correct??

  • Vishwas,

    TR = 0.35/BW is a rule of thumb (approximation) but I do not believe you applied it correctly to the TL082.

    TL082 stats.
    13 V/uS
    Risetime 0.05 uS (of unspecified amplitude)
    BW = 3 MHz
    ACL (AVD) = 200,000 V/V

    For UGB = ACL * 0.35/tr = 200,000 * 0.35 / 0.05uS = 1400 GHz
    3MHz is not close to 1400 GHz
  • hello Ron

    this is not related to this post but still i am posting here because i am not getting reply to the new threads that i have created and u are only who is giving quick reply to me....

    in the two stage op-amp ,while calculating bias current we use this formula  right   i=Cc * (dv/dt)   Cc->compensation capacitor    dv/dt-slew rate specification

    usually according to the miller theorem,let us assume  Cin is  at the output of first stage  Cin=Cc*gm  *Rout 2    [Cin=Cc(1+Av)]    where gm is the transconductance of the second stage and Rout is the output  resistence of the  second stage.   our Cin increases Av times the Cc as per Miller theorem.

    why we are not considering Cin for calcuating bias current   as   i=Cin*dv/dt   instead we are using Cc in the bias current calculation.

    regards

    vishu.

  • Vishu,

    The Cin equation is good for compensation pole cutoff frequncy 1/(2*Pi*Zout*Cin).
    For slew rate, the error amp provides a current to charge a virtually large CIN but small & slow input only applies during the active gain of the transistor and the transistor has gain in proportion to Av therefore Av nearly cancels out. This is why Av is not used in first equation.
  • hello Ron

    i did'nt understood sir....can u please elaborate or attached some reference pdf..

    regards

    vishu

  • hello Ron

    can u please elaborate?

    with regards

    vishu.

  • Yes, I will respond. I have a large backlog currently and will answer soon as possible.
  • Vishu,

    Here is slew rate for 10uA, 10pF, Av=-100.  Effective CIN = (1-AV) * 10pF = 101 * 10pF = 1.01nF;

    Slew rate = I / C * Av / (1 - Av) = 10uA / 10pF* 100 / -101 = -1V/uS = 0.9901V / uS

  • hello Ron

         while calculating  slew rate why u have taken  Av/(1-Av) ?  it should be this right -> Slew rate = I / C * (1 - Av)  

    that is --> slew rate=10u/1.01n=0.01 v/u S

    how does this  Av/(1-Av)  came sir bcz we need to consider only input side cap Cin=Cc *(1-Av)

    Sir why you are considering   the output cap  Cout=Cc *Av/(1-Av)     in the slew rate calculation i.e Slew rate = I / C * Av / (1 - Av)?

    Anyway by modeling the graph that you have got,i understood that.

    still littlebit   doubtfull  thats y posting here.

    regards

    vishu

  • hello Ron

    i hope u got my points,what i want to convey.....

    regards
    vishu
  • Hello Ron 

         I did'nt get any reply...........Plz clarify my doubts as soon as possible once you are free...

    regards

    vishu

  • Hello Ron

    please find the website reference below for which i would want to clear my doubts.

    analogictips.com/measuring-opamp-open-loop-gain-spice

    i have simulated the op-amp in the configuration to measure the open loop gain that is given in the first figure of the above website ...

    even i done the simulation on it.....when i performing transient analysis to check open loop gain, i observed that my output dc level is same as the input dc level for my all input common mode range.....So here are my some doubts please clarify on this..

    why is the output following the input in the op-amp which is configured to measured the open loop gain using RC negative feedback?

    What is the advantage of this topology ?
  • For DC results imagine all caps are removed (open) and all inductors are replaced by shorts.
    With this mindset, the amplifier is in unity gain so output should follow the input.
  • hello Ron

    As u said "amplifier is in unity gain so output should follow the input" if its that case then why the input signal is amplifying with open loop gain....
    Regards
    vish
  • Op-amps always amplify with open loop gain. The output is fed back to inverting input to oppose the input signal for the appearance of no gain (0dB). The web page circuits only work for Spice simulation. In real life, the input voltage (Vout/open loop gain) is so small reading it would be very difficult.