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why the P MOSFET output is not as expected

David888888
Intellectual 420 points

Please help.

I have designed a discrete power switch as in the attached TINA simulation model.

What I expect is:

When VG1 is high (5V), VF3 is low and VF4 is high and the output should be +5V instead of +12V.

But the simulation result is wrong as below:

when VF3=low and VF4= high, why T1 is conducted and the output1 is showing +12v?

Please help me to find the reason for this, many thanks.

David.

nnd.TSC

  • 0
    TI__Guru* 93105 points

    Hi David,

    The drain of T3 is pulled low to near 0 V in the circuit, which puts the gate of T1 at 0 V too while its source is tied to the 12 V rail. T1 is an P-channel enhancemnt MOSFET and a 12 V gate-to-source voltage turns it fully on. Since you have 12 V on its source and aren't pulling any current out the drain, the MOSFET develops very little voltage from the drain to source The dain pulls very close to the 12 V rail.

    If you add a load resistor at each of outputs to ground, you will source current through the T3 load resistor to ground. Then, you will see that the voltage doesn't pull all the way up to 12 V. The ON resistance of MOSFET will develop a drop across the drain to source. Try changing the input generator to produce a +4 V step on the input of T4. That voltage should be enough to turn T4 on and turn T3 off. Run a transient analysis and you'll see things switch in the circuit.

    So the circuit is behaving just as you have set it up to do.

    Regards, Thomas

    PA - Linear Applications Engineering