OPA170-Die: Wire-bonding

Yes, I too would like to know if there is any advisable sequence to be observed when wire bonding this product.

I suspect you may have some equipment issues.  If I assume you inspect the die after bonding and see EOS damage you need to check that all proper ESD Handling precautions are in place, along with all personnel ESD protective gear, and handling and all Wire Bonding equipment is operating as grounded for ESD. If you see no EOS damage after bonding but it occurs when you use the device send in your schematic and we can analyze further.  There is no 'magic' bonding order for OPA170 or any other die.  Billions of die have been served EOS free and all are wire bonded with no magic bonding order.  Let me know how else I can help.  

Thanks for this reply. Our investigation have indeed whitewashed wire-bonding as the source of ESD failure. In terms of the schematic that one was first validated with a PCB using only packaged components. In this configuration no ESD failure have been observed. However, once we started using bare dies assembled in a ceramic package, this is when systematic ESD failure started to occur. So rather than looking at the schematic level as you suggested, could there be differences at the packaging level? What specific precaution have you taken on your package assembly of the OPA-170 die? May input impedance changes between your way of packaging and ours potentially affect ESD failure?

ESD failure has been determined by looking at the I-V characteristic of each pads vs. the power supply rails. In case of ESD failure that characteristic appeared to be linear with a resistive path as low as 5-8 Ohm.

These devices have been tested at several stages in the assembly line: after die attach and after wire-bonding. No ESD failure has been observed at both of these stages. Because of lack of lid sealing process availability at the time, it has been decided to skip that process and go directly to the mounting of these components in test socket. Insertion of these LCC-44 package into test socket in absence of a lid is indeed tricky, but ESD handling care has been observed. Despite that there are lots of other active dies inside this package (and some presenting lower ESD protection threshold than the OPA-170) none of them were affected by ESD failure while systematically (100%) the OPA-170 was.

I understand that transistors have light sensitivity and that some specifications like offset might be degraded. This should however not affect ESD protection. Furthermore, at this stage, my only intend was to validate the full board functionality without going into full performance evaluation.

While ESD handling of the device during insertion in the socket might still be a candidate as possible root cause, I would still like to understand if there are additional care that would need to be taken at the packaging level. I'm mainly thinking about care to be taken about input impedance or die backside connection. Can you comment on this?

I am confirming but from datasheet I suspect ESD didoes to each power supply on +IN, -IN and Out.  Back side is connected to V- when used in normal packaging. V- to V+ will have some sort of SCR or snapback ESD protection device which shorts the rails together on a fast nanoseconds type transient.  I am researching for more details.  Can you provide any more details on when the parts are getting damaged?  After your first test after assembly?  I think you have a large risk and many possibilities if the final assembled part is not lidded or cover in light blocking goop. 

If you want a second look at your circuit for any weak spots I can review your detailed schematics.  If you are concerned about confidentiality I can give you my direct email address and we can take this offline.

I'm somewhat surprised to see your recommendation for the backside of the die to be connected to V-. Indeed, the die datasheet specifies the backside as being at a floating potential. Can you comment?

At this point, I'm still suspecting that the ESD failure occurs only when the die is powered on. However, there are some I-V characteristics which I don't know how to read. Indeed, I sometimes get a typical diode characteristics, but not a very sharp transition as is normally the case with ESD protection: in the conducting state the slope corresponds to an equivalent resistance of 2.7 kOhm, while the Vth is at 0.7V. If you could provide me with typical I-V plots of good ESD circuit and a failing ESD circuit, this would be helpful.

I am double checking on backside of die.

Your quickest answer for pin characteristics is to repeat your measurements on one of our packaged parts. 

We have no history of field returns coming back with ESD damage on our packaged OPA170.  Again, in the interest of eliminating variables,  I would encourage you to consider sharing schematics for our review.

Can I please ask you to take this discussion further off-line? Can you provide me with your e-mail address and eventually your phone number?

Thank you!

Best Regards

You can email me at t-green1@ti.com