INA3221: How to disable Power-Valid alerts in registers?

Hello Eric,

Thanks for considering to use Texas Instruments. To prevent the Power-valid alerts from triggering, I would set the power-valid upper register to 7FF8h and the power-valid lower register to FFF8h.

Could you provide an oscilloscope shot of the bit stream between the microcontroller and your INA3221?

Hi Patrick,

As far as I understand the datasheet, setting the upper register to 7FF8h means that all the voltages of all IN+ inputs must be above this value (see datasheet 8.6.2.17 and 8.6.2.18). So, if the IN+ inputs are at 0V the alert is always on!

if I set the upper register to +3V and the lower register to +2V, then the alert pin will be HIGH if all IN+ inputs are above +3V (no alert) and will go low (alert) if all IN+ inputs are below +2V. The upper and lower register form a hysteresis. -> the IN+ inputs have to be above the hysteresis to be "good". I tested this with positiv values in the upper an lower register and this works fine, but it looks like it's not possible to set negative values.

I checked with an oscilloscope. Unfortunately I do not have a scope with "print" functionality at hand. The Sequence looks like below:

Writing to the register:

1000'0000'0 | 0001'0000'0 | 1111'1111'0 | 1111'1000'1| -> Write 80h | 10h | FFh | F8h

Reading from the register:

1000'0000'0 | 0001'0000'0 |  -> Write 80h | 10h

1000'0000'0 | 0111'1111'0 | 1111'1000'1| -> Read 80h | 7Fh | F8h

To verify my code I tested the same sequence with the Channel 1 Critical Alert Limit register (07h). Here I get the the correct value returned (FFF8h).

It looks like the first bit of the power valid registers are fixed to 0!

Can you confirm?

Eric

Hello Eric,
You are correct; I told you the opposite of what you should do in the last post. Sorry about that.
At the moment, I do not have an INA3221s on hand and cannot verify on the bench right now. However, I did request some to be shipped to me last Friday and they should be here within the next day or so.
With regard to your reported bit stream, I noticed that you always receive a knack at the end of a read or write transmission. I would expect that you should see an acknowledgment, with the receiver pulling low at the end of the write transmission. Do you also observe this behavior when you write a positive number into the power-valid register?

Hi Patrick,

No problem! I'll have a look at the nacks till at the end of the read / write transmission. I'll let you know what my findings are till the end of the week. 

Thanks!

Eric

Hello Eric,

Any luck with converting those nacks to acks?

I finally got an EVM and was able to do some tests. Turns out you cannot change the 15th bit to 1 for either power-valid limit register. After looking back at the device specifications, this makes sense as the power-valid registers are actually assessing the voltage on the bus pins. Based of the electrical characteristics table, this device should be operated between 0V and 26V. The device can go as low as -0.3V on the bus pin before breaking, but this is in the non-linear region of device operation. So I believe the sign bit in the table may be something we will be fixing in the datasheet.