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INA240: +/-IN independent of VS

Guru 54027 points
Part Number: INA240
Other Parts Discussed in Thread: INA282

If the +/-IN pins are truly independent of VS supply why is there an intra-phase common mode limitation of only 80v? Specifically if monitoring current intra-phase, how can +/-IN pins CMM ever rise above the very small drop of typical shunt values? Has the laboratory ever determined +/-IN insulation package breakdown voltage when the 240 is placed in-phase? Have they ever tried to see if a few parts blow up to verify +/-IN are truly independent of VS supply when 240 is placed in series with phase coil?

If the VS supply is truly independent of +/-IN pins does that not constitute +/-IN pin isolation barrier exists between the differential amplifier? Seemingly ground is isolated from +/-IN as the datasheet infers or VS current flow would not be possible. Therefore +/-IN would be isolated from typical ground to phase voltage levels, when 240 is placed in-phase B+ is >80vdc.  Otherwise how are +/-IN pins made independent of VS supply not a false narrative under all possible mounting positions? Especially when there is no electrical proof or CUT to back up this odd claim....

Given 240 circuit CMM voltage may vary relative to circuit placement, why does datasheet AMR indicate +/-80v under all placement conditions? Seemingly the lower 80v CM might vary well be 1KV when 240 is placed in series with phase, if +/-IN are independent of the VS supply...

  • Hi BP101,

    Can you sketch a simple drawing to illustrate what intra-phase is, and label what you think the CM voltage should be? This will help me understand your issue better.

    Although you raised many questions in the post, the central one seems to be about whether CM range and supply voltage is truly independent from each other.

    The answer to this question is – yes they are independent of each other within the absolute max spec; and no, input pins are not isolated from the rest of the IC. These two aspects don’t contradict each other.

    From the CM input range stand point, INA240 is no different than any normal IC, except that its input range is extended beyond the supply with special circuit techniques.

    Regards, Guang

  • Hi Guang,

    The datasheet CM facts were seemingly taken from past INA circuit positions (low/high side), never when mounted in/intra phase. There is no GND reference on shunts +/-IN pins when devices are mounted in-phase, only current flow across the shunt. Likewise it is expected the +/-IN are truly independent of VS supply rail as top of datasheet suggests without any further electrical constraints being elaborated under certain placement conditions. Seemingly a far stretch datasheet to make any such claim as the +/-IN are then NOT exactly independent of VS supply, especially when device is placed Low/High side. Example being low side shunt transients end up riding on the VS rail pin, that is not independent behavior. Such behavior is not expected to ever occur when INA is placed in/intra phase, being the entire reason to place current monitors in phase.

    The +/-IN pins isolation barrier likely switched capacitor might easily exceed CM value 90V MAX relative to GND pin then becoming a (floating) reference to VS, relatively speaking. Otherwise the +/-IN are isolated above any GND reference, e.g. (in-phase). How is CM being limited to only 90V MAX for in/intra phase placement when there is no ground or B+ reference relative to +/-IN pins?

    Otherwise the +/-IN is NOT fully independent of VS supply as the datasheet suggests and is a false narrative in several provable ways? The word Independent infers not linked to a specific other or associated with or to any counter part/s. Again has TI ever attempted to verify in-phase mounting seemingly changes the entire CM datasheet narrative? Why has TI left the community to fall victim to low/high side placement via 90v CM MAX when seemingly INA should work up to the break down voltage of the +/-IN structures?
  • Hi BP101,

    As explained in my previous reply, here is the exact text from the datasheet:

    It clearly states that common mode voltage  is independent from supply voltage, with the restriction of -4V to 80V. The datasheet never makes the claim that INA240 is fully independent of Vs enabled by isolation barrier.

    Regards, Guang

  • Guang Zhou said:
    It clearly states that common mode voltage  is independent from supply voltage, with the restriction of -4V to 80V.

    Point is the in-line phase CM is very low often <200mV since there is no ground (neutral) in a WYE or Delta motor winding and NO high/low side reference for CM data is ever established. So the -4v to 80v CM is a non valid point for in-phase placement and only valid for high or low side device placement. The only time in phase CM is relative is only to the shunts voltage drop (E=IR) which will only see a few hundred millivolts MAX, unless +/-IN is not actually independent of VS.

    Series in phase CM needs to be determined by TI testing >80v phase voltage, say >200v. Perhaps the customer blowing up devices is not the best science approach.  Series in phase CM does not exist as it has been past defined and established by other high/low side INA device placement relative to high voltage B+ and Ground, not the VS pin alone!

    It seems to me that if we assume the datasheet to be correct (CM 90V MAX) infers questionable data for in series phase placement. Otherwise VS is dependent of CM and not isolated from current flow +/-IN to ground and or VS pin current migration from high voltage B+ paths that should not exist after in-phase placement. The idea of in phase series placement seeks to eliminate EMI, add PWM isolation from MOSFET switch node current transients that often occur from INA series devices placed parallel to DC supply. Parallel placement 240 still amplifies numerous switching transients that are not the actual phase currents.   

  • More to the point the INA "in-phase placement" is in series with DC high voltage supply confusing the CM topic. For low/high side placement INA in parallel with high voltage supply and CM 90v MAX makes sense.
  • Guang Zhou said:
    From the CM input range stand point, INA240 is no different than any normal IC, except that its input range is extended beyond the supply with special circuit techniques.

    So TI abandoned the INA282 50Khz switched capacitor isolation (+/-IN) front end input to the differential amplifier of the 240. That is one reason for believing CM might behave differently when 240 is mounted in series with HV supply. The VS +/-IN pins of series placement should be independent, AKA isolated from typical CM voltages that are encountered when 240 is placed in parallel to/with both VS and HV supply current sources.  

    Plausibly the datasheet analysis has not defined a restriction of CM actually exists for series in phase current monitors. As it relates to VS pin isolation being either dependent or independent from CMV for specific device placements relative to HV supply on +/-IN pins. That's why laboratory test the +/-IN voltage >90v, perhaps define a separate much higher CMV exists for in series phase mounted devices, also a lucrative marketing point if it is true!

    The series phase coils are in series to +/-IN pins adding to the input resistance, in our case 1.1 ohms + 5mOhm shunt. Would like TI to confirm the 240 +/-IN can survive 200v in series placements where CM drop across shunt seemingly ever has a few hundred millivolts. CM seemingly can never reach above shunts voltage drop being a few hundred millivolts and not 90V MAX as datasheet AMR seems to imply. The only time HV is present on +/-IN is relative to ground when measured via DMM or oscilloscope, a differential probe might better indicate the actual in phase CMV (float) is safe >90V.   

  • Hi BP101,

    We’ll be more than happy to confirm the feasibility of our device in your application.

    However, please do us a favor and draw it up in a diagram to illustrate your use case. It will save everyone’s time by avoiding ambiguity and misinterpretation.

    If such confirmation requires lab test, we’ll try our best within our capability. The only requirement for you is to clearly define the issue at hand.

    Regards, Guang

  • Guang Zhou said:
    The only requirement for you is to clearly define the issue at hand.

    Not sure how much clear I can be and updated testing involves the typical use picture first page of datasheet. Again the AMR in datasheet CM=90v MAX was most likely determined for high side, not in-phase as the typical use application shows. Notice how the typical use shunt is in series with HV supply, versus being in parallel for high/low side placement? It would seem a likely deduction a differential probe placed on the typical use shunt would prove the drop never exceeds several hundred millivolts as HV phase supply moves from 80v-200v. If typical use shunt does exceed ohms law (E=IR) mV drop, the VS pin is not exactly acting independent of +/-IN pins even up to 90v CM. Notice a comma was placed between the first and second part of the sentence you posted. 

    Again there is no datasheet CUT showing how the lab arrived at CM 90v ever being possible for in-phase placement. However if there is an unknown High current path to ground via +/-IN pins that might explain why low side switching transients are so extreme for the 240 die. Extreme beyond -4v specification when REF1/2=GND or REF2=mid-supply, REF1=GND. Obviously we are currently stuck with the first option, full scale from GND to 3v3.   

  • Hi BP101,

    The INA240 cannot be used as shown in the schematic, due to the fact that the DC bus voltage of 170V is over the common mode input range of 80V. In this configuration, the INA240 sees a varying PWM input common mode voltage between ~0V and 170V.

    You’re correct that the differential input voltage, ie the drop across the shunt resistor is no more than a few tens to hundred mV; however it is the common mode that is the problem.

    Regards, Guang

  • Guang Zhou said:
    You’re correct that the differential input voltage, ie the drop across the shunt resistor is no more than a few tens to hundred mV; however it is the common mode that is the problem

    Yet Tina DC analysis indicates no common mode voltage of that magnitude on either side of the in-phase shunt. Besides what datasheet refers CM 90v is seemingly the break down voltage of the +/-IN structures relative to GND, whether independent of VS or not. Shunt VOS seems all that is present in transient/DC analysis when MOSFETS and indictors are added to the PWM simulation.

    That said if CM ever reached >90 across the shunt it is occurring due to the internal design of the 240. Perhaps the die has undocumented excessive leakage current through the +/-IN pins into VS or GND pins? If we check current flow for the resistor values into GND via REF1/2, 1.6mA is the expected leakage current (A1) and package thermal dissipation is very small (272mW) at 170vdc. That of course without any PWM filter shown in the diagram below, would add even more resistance to the inverting/non-inverting amplifier inputs.  

  • Hi BP101,

    What is your question?

    Regards, Guang

  • You said the CM would be >90v yet Tina analysis indicates the DC/AC on either side of shunt as 1.43v for 170V DC as noted by the VG1-170. That is another reason to question why the in-phase placement would ever present an issue? Transient analysis seems to arrive at the same conclusion there should be little to no leakage current into +/-IN pins for supply voltages >90v. Can you prove that idea is not correct using Tina?

    Note: Current of R11 could not be 1.3A if 170v was not present. Voltage is considered the electrical pressure behind and causing current flow, not the result of current flow. Current AKA (electrons) will seek the least resistive path to ground, though often it is incorrectly stated as being voltage. That least resistive current path is through the inductors L1/L2, not the 240! What we need to know is the BV of +/-IN relative to 1.6mA of expected current through 240 producing additional package wattage!    

  • Hi BP101,

    Can you do a transient analysis and plot VG1, voltages on INP and INN?

    Regards, Guang

  • Hi Guang,

    I already anticipate what you might conclude. Again VM1 measure is only relative to the external analysis ground point of VM1, not a current path through 240 via GND/VS/REF1/2 pins. So the Tina transient analysis is bugged by that aspect alone. Tina is not intuitive enough to determine a break down CM>90v +/-IN will ever occur in this circuit. The only way CM can exceed 90v is relative to external ground paths that should not exist (in-phase) through the 240! Otherwise if it can exceed >90V CM +/-IN pins perhaps there is to little isolation on the front end of the PWM input filter and dv/dt can plague any parent circuit as VM1 indicates -170v inductive kickback relative to GND.

     

  • Hi BP101,

    The inverter stage and INA240 share the same ground.

    The TINA circuit represents part of a BLDC driver. You’ll need to have both top and bottom witches in order to see the actual PWM action. However, it should be enough to convince yourself that INA240 sees the full 200V at some points. You can read this app note for basic understanding a current sensing in motor drivers.

    http://www.ti.com/lit/an/sboa172/sboa172.pdf

    Regards, Guang

  • Guang Zhou said:
    However, it should be enough to convince yourself that INA240 sees the full 200V at some points

    It's what the datasheet does not say about package thermal dissipation and +/-IN pins breakdown voltage makes the question viable. Datasheet CM parameter seemingly proves circuit design in-phase placement is not so much independent of VS if +/-IN pins react to other circuit criteria other than a shunts voltage drop. Proof of this issue noted by REF1/2 pins being grounded, the output still swings below GND rail allowing transients to enter the SAR. No wonder all TI motor current monitor example circuits set 1.65v mid supply to avoid transients from -4v swing below GND rail. That -4v swing has not been properly characterized in the datasheet and remains no matter how REF1/2 are configured. That -4v swing below GND rail is a real conundrum! This is only the 21st century, maybe 22nd generation will have figured out how to properly isolate current from voltage monitoring.

    Guang Zhou said:
    The TINA circuit represents part of a BLDC driver. You’ll need to have both top and bottom witches in order to see the actual PWM action.

    Still not convinced the external circuit voltage should be an issue if the +/-IN pins have no AMR breakdown voltage. Datasheet has not provided typical industry CUT for presenting necessary circuit design facts, "Tina analysis above indicates" relative to any +/-IN pins silicon dielectric barrier being at all independent of VS or any other package pin. Just saying something does not may it true or real without providing proof which Tina is not capable of producing!

    Lastly why did Tina transient analysis above post not show the +/-200v on the OUT_A1 or the VS pins?

  • Please provide a Tina analysis that proves CM>90 +/-IN pins will cause 240 device destruction when placed in line. Again current takes the path of least resistance to ground being the external circuit inductors, not the INA240!

    If shunt CM>90V destroys the 240 there is excessive leakage to GND where it should not ever be any greater than the inductors being measured in the shunts drop. The circuit inductors always present the least resistive path to ground. Otherwise silicon breakdown voltage on the +/-IN pins voltage isolation barrier is the issue, not CM.

    Typical electronics theory is being violated by 240 and other INA devices....
  • Hi BP101,

    When the common mode range is violated, the INA240 TINA mode ceases to work, like below sim shows.

    Two cases are compared, Vcm=70V and Vcm=120V, all other conditions are identical. The differential input should produce a 5V full scale square wave when INA240 works properly (Vcm=70V).

    Regards, Guang

  • Seemingly your model measures reverse current flow from battery into -IN pin into VMD. Where is the inductors least restive path to ground being modeled? Tina can not be trusted to show how the laboratory derived CM>90v is the cutoff point. Perhaps trapezoidal setting produces a different outcome in your model? One book states if it don't smoke or explode the package up to a certain mid point for several hours that is also good proof.

    I understand your point CM across the inverter being >90v via external GND. Yet if the 240 dissipation is not effected in a bad way how can CM>90v destroy +/-IN structures? Perhaps something else is affecting +/-IN as CM>80v and also leads to unexpected output artifacts via low side monitoring? Note we discovered the size of a motor effects the 240 output. The more magnets motor has the more CCEMF transients affect the SAR ability to handle the nefarious unrelated signals!

    Inductive CCEMF transients NOT part of shunt voltage drop, above and below ground plague the 240 output! It seems as VS bypass is increased from 100n to 10000n the 240 output gets quieter, CCEMF transients remain. The resulting signal trashes SAR below ground and above 3v3 (VS) shunt drop signal regions! The 240 VS pins being isolated from SAR via dedicated 3v3 LDO only reduces CCEMF artifacts. The only other alternative in to mount the 240 in-phase to remove incorrect inductive CCEMF!
  • Your model with REF1/2 GND produces different results, Gear/Trapezoid no matter. Tina 240 spice model can not be trusted to prove +/-IN breakdown voltage being exceeded, >CM 90v. Have to do a crash & burn test to see where IN pin breakdown voltage occurs or other parts of dielectric barrier become unstable. Other competition datasheet typically list dielectric barrier (700v-1Kv) or more may be expected and CM +/- 270v Max.  

  • Hi BP101,

    We’ll not match 270V common mode, and will not do such test either. It is out of the question. However, you have the freedom to use the part in any way to your pleasure. As long as INA240 remains in the specified range as detailed in the datasheet, it is covered by TI warranty and policy; otherwise, not.

    The model stops working once the CM range is violated, this is done intentionally so that hopefully the user is prompted to look for the reason why the circuit is not behaving as expected. And this is the way the models is telling you that something broke.

    Regards, Guang

  • Guang Zhou said:
    The model stops working once the CM range is violated, this is done intentionally so that hopefully the user is prompted to look for the reason why the circuit is not behaving as expected

    Oddly my model proved your model was just as wrong and VMD caused your model output to invert.

    Guang Zhou said:
    However, you have the freedom to use the part in any way to your pleasure. As long as INA240 remains in the specified range as detailed in the datasheet, it is covered by TI warranty and policy; otherwise, not

    It would seem the datasheet leaves out a few important details regarding PWM transients. One fact omitted being the number of motor poles directly effect the 240 setting times as trapezoidal transients increase with motor speed. Our case 36 poles PWM transient rejection reduces at very low speed and output takes 400us to be considered settled to 1/2 LSB via SAR ADC. Where 12 poles produces very different results setting 2.5us very high speed.

    Such behavior is not being conveyed by datasheet tested artifacts graphs of CMRR or PSRR and the most important artifact CCEMF is completely ignored.    

  • Hi BP101,

    We are beating the dead horse here, the model will not work when common mode is violated. There is really no point to dwell on this much longer.

    As far as why your system response time varies with different motors, I really can’t say much about it one way or the other because every system is unique. I’ll be happy to help look into this if you can isolate the issues and demonstrate that INA240 itself is the root cause.  

    Regards, Guang

  • Guang Zhou said:
    As far as why your system response time varies with different motors, I really can’t say much about it one way or the other because every system is unique.

    Yet you say to other poster motor type poles count affect output settling. Well anyway the Drones PDF specify 0.500ms settling in our 1ms(1kHz) closed loop speed PI. That 0.5ms, e.g. 500us settling aligns with 400µs to 480µs we must set for SAR settling, value is way outside datasheet specification.

    In-Phase monitor removes some part, not all CCEMF (flyback) from distorting output settling times in SAR ADC? Why does 240 output settling become a multiple well above typical PWM frequency <20kHZ 50us? The 400µs settling we see occurs low PWM 12.5KHz (80us) periods and seemingly linked to poles count and or motor voltage >24vdc. It seems to me there is an undocumented datasheet value in the 240 output settling times which is removed via in-phase monitoring?

    The TI SAR ADC samples 240 output @2MSPS and any settling time configured <400µs produces very low and incorrect current measures.