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INA3221: any layout guideline for IN+/IN- pins

Part Number: INA3221
Other Parts Discussed in Thread: INA190EVM

Hi Experts:

I was doing NB design with INA3221.

But I cant find any layout solutions for the parallel sense back pins.

could you help to point out anything I need to take care?

ex. parrallel layout, isolating distance, how many mils I need to have for my wire?

so many thanks,

  • Hey Ted,

    Welcome to the E2E forum.

    Could I get some more information on what you are trying to accomplish? Are you referring to parallel traces for IN+/IN- pins of each three channels? Are all the traces coming from different shunt resistors? What wire are you referring to when questioning how many mils are needed?

    The general guideline is to treat the IN+/IN- traces as a differential pair. This means you want to route the traces close together and in parallel with each other.

    Sincerely,
    Peter Iliya
    Current Sensing Applications
  • Hi Peter

    Actually we are designing 4 INA3221 for all load switch path(all power system…3V,5V…etc), every power path we are having a shunt current .ex: 3V is seperating to 3V_WLAN/ 3V_CAM/ 3V_Thackpad…etc. we would like to sense back every path, but not sure if any specific rule I need to follow, or just use the normal sense line rule?


    so normally the rule I will propose:

    1. 8 mil width wire for each IN+/IN-, and rule followed differential pair.
    2. Isolation Trace Spacing between IN+/IN- will be 10
    3. Avoid any BUCK_SW signal crossing IN+/IN-
    4. Via number for IN+/IN- less than 4.
    5. shorter trace as much as possible.

    (basic rule that I used to have.)
    another suggestion, pls help to review, thanks.
  • Hey Ted,

    I think the rules you have enumerated are very reasonable for this use of INA3221. I suggest also heeding the instruction of the Layout Guidelines in datasheet Section 11.

     

    I would say a couple other additional potential rules are:

    -  If space allows and filtering noise glitches is critical to your design, then place a landing pad for an input capacitor in between IN+ and IN- pins. This capacitor should be as close as possible to input pins of INA3221. This could help dampen any high-frequency current transients required by system load. Even though it would take a large amount of current to create a significant shunt voltage transient, having the pad allows for any potential design tweaks/hardware debug needed later.

    - Gaussian noise can be filtered by setting the INA3221's internal averaging mode.

    - If noise is very high in your system and needs to be reduced further, then consider guarding your input traces. This means routing traces adjacent to IN+/IN- traces. Usually the shielding traces are at ground potential (0V). The shielding traces shield IN+/IN- from capacitively-coupled noise. This rule is over-engineering and usually unnecessary, but it is an option for certain noisy applications. This layout was used in the INA190EVM, bottom left panel.

    http://www.ti.com/tool/ina190evm?keyMatch=ina190evm&tisearch=Search-EN-Everything

    Hope this helps

    Sincerely,

    Peter Iliya