INA128: input is observed a negative overshoot voltage with long settling time if Vs-=-5V

Joyce Li

Part Number: INA128
Other Parts Discussed in Thread: OPA177

Hi dear expert,

We met an issue when using INA128. Vs+=5V, Vs-=-5V, during the power supply ramps up, the input pin can be observed a negative voltage overshoot down to -1.7V and will ramp up very slowly to 0V, the ramp up time can last 2 seconds. Below snapshot is from input pin:

If we make Vs-=0V, the input pin will be not seen such a big negative voltage and the settling time is also shorter, around ~10ms. See below pic with VS-=0V.

The schematic is as below: INA128 is the middle device.

Our questions:

1. is this phenomenon is expected? and the input negative voltage is generated from INA128?

2. Is there any way to make the settling time shorter to xxms?

Thanks a lot for your reply.

Joyce

over 5 years ago

0 kai klaas69 over 5 years ago

Guru 140200 points

Hi Joyce,

very hard to decipher the schematic...

Do you violate the absolute maximum ratings during power-up? And, are the input voltages or the REF voltage outside of the recommended range?

Kai

0 Joyce Li over 5 years ago in reply to kai klaas69

TI__Intellectual 2170 points

Hi Kai,
Vs+=5V, Vs-=-5V. it is within the recommended range. You can save the pic and zoom in to see clearer.
Any idea?

Thanks.

0 user5897811 over 4 years ago in reply to kai klaas69

Prodigy 30 points

Hi Joyce,
There are two points that need to be added.
(1) In Figure 2, V- is not 0, but is floating.
(2) Figure 2 shows the phenomenon after the magnetic beads are removed, but this phenomenon is the same as that of the other INA128 circuits on the board (the same). In other words, the delay of other INA128 circuits on the board is not as long as that of Figure 1.
So,what is the delay related to?

0 Joyce Li over 4 years ago in reply to user5897811

TI__Intellectual 2170 points

Hi Kai,
User5897811 add more add more comments on this issue, hope you can take a look and give us reply
thanks.

Joyce

0 Tamara M Alani over 4 years ago in reply to Joyce Li

TI__Genius 10850 points

Hi Joyce and User5897811:

The schematic is a little challenging to read and understand, even after zooming in. Do you have this built in TINA Spice?

In the first configuration, you have Vs+ = +5V and Vs-= -5V, is that correct? What is the REF? What is the gain? What is the input signal?
In the second configuration, you have Vs+ = +5V and Vs- = floating, is that correct? What is the REF? What is the gain? What is the input signal?

-Tamara

0 kai klaas69 over 4 years ago in reply to Joyce Li

Guru 140200 points

Hi Joyce,

I agree with Tamara. The schematic is totally incomplete, even when zooming in. :-)

What I can say up to now is, that all the ferrite beads should be removed. Instead, mount proper decoupling caps to all the supply pins.

Kai

0 user5897811 over 4 years ago in reply to Tamara M Alani

Prodigy 30 points

We designed this circuit to build a PGA circuit. The block diagram is as follows.

The default state switch (RF Switch) of the board design is not connected to the previous stage. It is equivalent to the following figure. All tests are tested in the default state.

In the figure: RG = 287 Ω;
REF: Connected to the zeroing circuit of the latter stage, but did not use the OPA177 op amp, using other company coded op amps.

0 Tamara M Alani over 4 years ago in reply to user5897811

TI__Genius 10850 points

Hello User 5897811:

Unfortunately, your photos did not attach correctly so I cannot view them.

Did you try what Kai suggested? "all the ferrite beads should be removed. Instead, mount proper decoupling caps to all the supply pins."

-Tamara

0 user5897811 over 4 years ago in reply to Tamara M Alani

Prodigy 30 points

I want to confirm with you whether the chip itself has this negative pulse problem.

0 Joyce Li over 4 years ago in reply to Tamara M Alani

TI__Intellectual 2170 points

Hi Tamara,

Please see below pic:

We designed this circuit to build a PGA circuit. The block diagram is as follows.

The default state switch (RF Switch) of the board design is not connected to the previous stage. It is equivalent to the following figure. All tests are tested in the default state.

In the figure: RG = 287 Ω;
REF: Connected to the zeroing circuit of the latter stage, but did not use the OPA177 op amp, using other company coded op amps.

0 kai klaas69 over 4 years ago in reply to Joyce Li

Guru 140200 points

Hi Joyce,

pleae keep in mind that you must provide a path for the input bias currents of INA128 to signal ground. See section 9.2.2.4 of datasheet of INA128.

Kai

0 Tamara M Alani over 4 years ago in reply to kai klaas69

TI__Genius 10850 points

Hi Joyce,

We haven't heard from you in a week. We hope your issue was resolved. I'm going to close this thread now. If you have more questions regarding this device, feel free to reply to re-open.

-Tamara

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INA128: input is observed a negative overshoot voltage with long settling time if Vs-=-5V