THS4520: Stability issue with gain = 0.95

Hello Maxime, 

You simulation seems correct - did you add those 5pF at the summing junctions - good job, that is a nice noise gain shaping point, I do that differentially. Points, 

1. I have learned to make sure we are using the most recent model - you had a 2010 model in your file, the online TINA reference design is 2011. I dropped that into the attached file (they reversed the supplies?? fixed that).No real change in phase margin. 

2. This is a very old model, it is possible that the open loop output impedance (that really messes up phase margin with feedback C) might not be in the model. Was trying to test that, no luck so far. 

The most recent efforts at FDA modeling made a meticulous effort to capture those effects, and yes they can cause a lot of problems. I have found inserting small series resistors inside the loop at the outputs can be helpful. Stepped through this in detail in this recent article, 

Your file with updated 2011 model,

2626.Full analog chain with gain - stability 2011 model.TSC

Hi Karan,

Thank you for your feedback. 

The input signal is a 2Vpp square signal at 5MHz. 

The purpose of C11 and C12 was to add parasitic capacitance to the circuit to see if I could make it unstable. I should have remove them before sending the TINA file. 

Even with playing with the value and position of C11 and C12, the simulation always gave me very good phase margin. I think it too good to be true, I am also thinking that the THS4520 model is wrong for simulating phase margin.

I'll see if I can send you the schematic.

Maxime

Hi Maxime, 

That was my theory - the model test I do showed no open loop Zol in the THS4520 - but these rail to rail out devices physically have a pretty peculiar Zol. I worked a lot on the THS4541 device and model - it does include that correct Aol, Zol and differential input Zi and a lot of other things - it is more reliable for predicting phase margin issues. How I do all of this detailed in a series of articles, 

This one is background info mainly, 

https://www.planetanalog.com/author.asp?section_id=3404&doc_id=565056&

 This focuses on the FDA, Using another part I worked on (device and model) the THS4551

https://www.planetanalog.com/author.asp?section_id=3404&doc_id=565122&

So yes the THS4541 should work, I did drop it into the circuit and it had ok phase margin. attached

1. I did not say the THS4520 would be stable, no idea with the poor model. 

2. Running inverting gain < 1.0 is no problem for any op amp or FDA. If there is a phase margin issue, that will show up in the LG sim where the "Designing attenuators" sections I put into the THS4541 and THS4551 datasheets tell you what to do to improve if necessary. 5417.Full analog chain with gain - stability THS4541 model.TSC

I was looking at your LG sim circuit again. Everything looks fine but you are using kind of odd split supplies. Normally the FDA will level shift I/O pins to be above ground and in range so that only maybe a 3.3V single supply is required for this type of app. (negative supply at gnd) That does come up regularly as a question, that I tried to answer in 2nd 1/2 of this article, 

https://www.planetanalog.com/author.asp?section_id=3404&doc_id=564993

So in the file where I dropped in the THS4541 into your original ckt testing LG phase margin, I got 58deg - which is fine how it is. Now if you wanted to model layout parasitics in that ckt, it might change. 

Hello Maxime,

Are you talking about the THS4541 - most sensitive nodes are the two outputs and input summing junction nodes.

Your output swing is your required swing on each side I think - and actually usually -1dB below that to avoid clipping for 0.95V input CM 2Vpp max input ADC,s. The physical output stage can run to about 0.2V within the supplies, so their headrooms are fine vs required. The input pins swing to the negative supply and have I think about 1.2V to the positive supply - usually not a limit

The CM loop is a completely separate circuit and swing range question. Yes, max 0.94 is close - which is why I usually look for a tolerance on the ADC input CM and shift it up some to get headroom

What happens when the CM control voltage dips to low to the negative supply is current mirrors start to saturate reducing CM loop gain and performance - giving both DC and AC errors.

I went into the ADC datasheet to see if I could find a Vcm range plot on the inputs, and yes - there is a nice plot in figure 21 showing this, I would say target 1V input Vcm setting the Vocm control at 1V for the FDA - also, if you have any series R from the FDA to the ADC, be sure to account for the sample rate dependent Icm current into the ADC inputs that will give you a small drop in voltage from the output Vcm at the FDA pins. 

Hi Michael,

Thank you.

I will use a voltage reference to provide 1V VCM to the FDA. Should I use the voltage reference to provide the 1V VCM to the ADC too, or should I let the ADC operate on its internal 0.95V VCM?

I thought the ADC and the FDA had to have exactly the same common mode voltage in order to operate properly. But after reading your comment and having a closer look on the ADC datasheet, it looks like the ADC can accept a -/+50mV variation around 0.95V on the input common-mode voltage (see datasheet extract below). Do you confirm? 

I have an additional question about the THS4541 measurement conditions for the output voltage headroom specification.  

The datasheet says that the worst-case output voltage high is Vs+ - 0.25V, and that the worst-case output voltage low is Vs- + 0.25V. 

My first question is: at what load current are specified these voltage? Datasheet says that typical condition is Rload = 499V and Vout = 2Vpp, which would give a current of I = 1V / 499ohm = 2mA. Can TI confirm this?

My second question is: do these voltages stay the same if the Vocm output common-mode voltage is not at mid-supply (typical measurement condition given in datasheet? WIll I still have 0.25V headroom if I use a 1V output common-mode voltage and a 3.3V/GND supply?

Thank you,

Maxime 

yes, the internal Vcm in the ADC is provided as a convenience normally to bias the centertap of a transformer coupled interface. You don't have to match it and there is some range on it 1.0V would be good, but really just using an R divider off of whatever other somewhat precise reference is available is good enough - just make sure some caps are there for noise. There is some forgiveness in the accuracy of the FDA Vcm output voltage.