Part Number: OPA820
I can not verify the Noninverting Pulse Response in our applikation.
VCC=6.2V...10V, VSS=-2V, Gain=+1, Pulse Signal High Level 4.6V, Pulse Signal Low Level 1V
Load: 50R series resistor+50R input resistance oscilloscop
Testboard TI DEM-OPA-SOT-1A
C1, M1, M2, M3: Output OPA820 for different VCC Values
C2: Input OPA820 (Generator)
Is the measured rising edge slew rate correct?
There is really hardly enough to go on here, a picture (schematic) would help Tina file preferred,
Essentially you need to arrive first at the small signal response shape to see what it to produce assuming a fast input edge (and what is that).
Some of the required layers are considered here,
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Also, would you be able to post the figures again; we are unable to view them.
In reply to SimaJalaleddine:
the additional informations:
The schematic is that of the TI demo-board.
C1, C2, C3, C4, J1, U1=OPA820, R2, J2 assembled
R1=100k, R6=0R assembled
all other components are not assembled
J1 is connected to the waveform generator, Output Impedance 50Ohm
J2 is connected to the oscilloscope, Input Impedance 50Ohm
Figure1, (C1) OPA820-Output at J2 Demo-board, (C2) wafeform generator at J1 Demo-Board
Figure2: expected pulse response (OPA820 Data Sheet)
In reply to user34641:
I am still unable to view the image/file; you can use the insert file or insert/edit media icon within the reply window. Follow this post to correctly insert a file or image: https://e2e.ti.com/support/site-support/f/1024/t/761613.
those larger step plots certainly look slew limited, be careful not to be clipping. Here is a more detailed pair of slew rate articles discussing the edge issues,
Thank you, it worked. As Michael mentioned, the large signal response looks slew limited in your application. Output saturation could be a concern for a rise in supply current. Would you be able to share the schematic using the same method? That seems to be the only figure missing compared to your original reply. Also, what is the range of your input signal requirements for your application?
the schematic is that of the TI demo-board.
The Input Signal Range is 1V ... 4.6V.
just ran a simulation: The TINA-TI reference design does not show an output voltage toggling any more with this low load impedance this high output voltage.
In reply to kai klaas69:
The sim of the modified EVM works fine,
It does show about 460Mhz SSBW - that is pretty fast for such a slow slew rate device.
Your measured plots look like they are labelled backwards, and are clearly slew limited. That single overshoot and decay is indicative of the loop opening as it slew limits then closing again to a final value.
The details of that edge shape also depend on the input edge rate which you have not reported.
What is the question again?
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