photodiode transimpedance for pulse (20ns)

Hello James,

    A couple of quesrions:

1. The OPA860 is a transconductance amplifier (VtoI) converter. For your application an opamp configured as a transimpedance amplifier would be more suitable.

2. The BW of a pulsed application is better determined by the rise/fall time of the pulse. Do you have a number for this? Once we know this we can determine how much BW is required.

3. You mentioned 2 gain paths. I assume you will have a switch to go from the low gain path to the high gain path. Is that correct? The problem really lies with the high gain path, wherein you need a lot more resistance(transimpedance) but would still like to maintain the bandwidth. This is going to be a challenge.

One thing for certain, on the high gain path you need a TIA with a JFET input, like the OPA657 & OPA659. The reason for this is that the alternative "bipolar input" amplifiers have a bias current in the nA-uA range which would drown out your input excitation current. Once we have narrowed down the design of this amplifier I would suggest adding a 2nd gain stage which would help you maximize your dynamic range. 

Will the output of the transimpedance stage feed into a high speed ADC? If so I would recommend using a fully-differential amplifier like the THS4520/THS4521. We can get to the fully-differential amplifier design later but it will be good to know this now so that we can optimize as we go along.

For the low gain stage the OPA846 may be sufficient for your application. We will need a transimpedance resistor of 3V/1.1mA = 3KOhm and the BW is based on the rise/fall time that you provide.

Samir

2. Rise Time = 3nS.

3. You are correct. I agree the high gain will be the hardest (0.1 uA).

4th paragraph: I was planning on having to cascade gain stages to achieve this, you are correct.

5th paragraph: Yes, end game is to feed the output into a high speed ADC, not chosen yet. For now we are just bench testing to prove out a solution.

Thank you for the help!

Note: I have a quad detector, so I prefer having a quad pack for suggestions, if at all possible, if not possible, then I will make due.

Hello James,

  With a 3ns rise time one would ideally like a BW of 0.35/3 = 116MHz. The BW of a transimpedance amplifier is based on a couple of factors:

1. The photodiode capacitance. (The higher this capacitance the lower the BW when all other parameters stay the same).

2. The Feedback resistance (Transimpedance).  (The higher this resistance the lower the BW when all other parameters stay the same).

&

3. The GainBandwidth of the Opamps. Here the higher the GBW the higher the achievable transimpedance BW when all other parameters stay the same.

Now, the only quad JFET Amp we have is the OPA4354, unfirtunately this doesnt have anywhere close to the BW we need. Even among our duals we dont have a part that is good enough. The OPA657 is our highest GBW JFET amplifier.

Ideally we would like to stabilize our amplifier with about 45degrees of Phase Margin. I have attached some TINA spice simulations on analyzed loop stability and closed loop BW for the Transimpedance Amp (TIA) application. I am also attaching an application note on stabilizing transimpedance amplifiers. TINA spice can be downloaded from the TI website. This is a good tool to do all the stability BW analysis, prior to doing real test on a PCB.

I have one TINA file called TIA Open Loop Analysis. This is for checking loop stability. In this circuit I have an ideal opamp configured as a TIA circuit with the PD cap. the feedback resistor and capacitor. The latter two our parameters we will change in order to get a balance of BW and enough phase margin (stability). I use this section of the circuit to simulate noise-gain (1/Beta). I also have the OPA657 with a large inductor and cap in a closed loop. This circuit simulates the Open Loop Gain (Aol) of the OPA657. When I run an ac simulation of amplitude and phase I also generate a calculated curve from the Noise Gain and Aol. The calculation is LoopGain =  Aol/Noise Gain. In order to estimate phase margin I check for the point where the LoopGain = 0dB magnitude and then check the corresponding phase. The phase margin is 180 - the measured phase.  See below.

In this case the PM is around 45 degrees. So at this point I have a stable configuration. Now I use the 2nd simulation file, "TIA Closed Loop AC Test" and run an ac sim to determine the closed loop BW. From the simulation I am seeing about 65MHz which about half of what was initially required.

So now the problem is do we want higher gain or higher BW. This is a tradeoff you will have to determine based on your system needs. There is an OPA847 which has higher BW but it has a higher input bias current which may not work for your low input current scenario.

7446.TIA Open Loop Analysis.TSC

8345.TIA Closed Loop AC Test.TSC

2084.TIAs for High Speed Applications.pdf

Please let me know if you have any further questions with regards to the design.

Samir

High Side Gain 0.1uA TIA 3V: I believe my plan will be cascading two in series and dropping the gain of the TIA in an attempt to increase the BW. In your model you had 20K Rf, If i use two stages and want my output to be near 3V when saturated then using a 5K resistor on both stages should be sufficient (TIA and then a op-amp). I will have to run the simulation to make sure everything is good.

Low Side Gain (mA): I will use your other suggestion of OPA846 to achieve the desired result. I need a TIA gain of 1.5K to achieve my desired effect.

Then I can choose which gain side I want depending on my input pulse.

Thank you for the help!