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3-Stage Amplifier with LMH6702

Other Parts Discussed in Thread: LMH6702, TINA-TI

Hi guys,

I have a 3-stage optical detector and amplifier using LMH6702 as depicted below.

I am using it for 20-50 MHz pulse detection.

The circuit with only the first two stages works great and I don't have any problem with that. But when the third stage is added, Vout for a grounded input is oscillating in a weird shape (at ~1.67 KHz) as follows:

Does any one have any idea what could be the reason for such a oscillation?

The circuit is implemented on PCB and I have considered all the design rules from the datasheet and application notes.

I greatly appreciate any help.

Thanks,

Moha

  • Hi Moha,

    I agree that the slow 1.67kHz waveform you are saying is truly strange for a GHz range amplifier like the LMH6702! I don't have any answers as to the cause, but here are my comments anyway, hoping they may help you troubleshoot the problem:

    1. Stage 2 Loading: I suppose Stage 3 is a harsh load for Stage 2 (heavy cap load to virtual ground on Stage 3). Is it possible to add a resistor in series between Stage 2 output and 33pF input of Stage 3, for testing purposes initially, to see if anything changes?

    2. Stand Alone Testing: What if Sage 3 is run from a lab GEN / Source instead of Stage 2 output? Have you tried that? I suppose using a triangular input of proper amplitude and frequency, should create a square wave at the output, if things work fine.

    3. Higher Stage 3 Feedback Resistor: Can you try increasing the Stage 3 feedback resistor (from currently 390ohm) to see if you can affect anything? Say 1kohm.

    4. Cap across Stage 3 non-inverting input resistor: Add a 0.1uF cap or similar across 39ohm in series with Stage 3 non-inverting input, for testing purposes first.

    5. Resistor in series with Stage 3 Inverting input: As last resort, if nothing else affects things, what if you inserted a 150ohm resistor in series with the Stage 3 inverting input (pin 2) so that the internal buffer (between LMH6702 pin 3 and pin 2) does not see a direct cap load (33pF to the Stage 2 output which is low impedance). My thinking here is that what if the buffer internal to the LMH6702, does not like to see a capacitive load and the resistor I'm talking about provides isolation.

    6. Loading Stage 3: Have you tried loading Stage 3 (say 100ohm to ground) to see if the waveform is affected?

    I admit the comments I've made above are mostly things to try if you have some high frequency oscillation, which you don't seem to have. So, I'm kind of shooting in the dark, but there is a possibility that you may have high frequency instability and the slow kHz waveform you are observing is an artifact of the device instability (although I've not seen anything like it before with the LMH6702).

    Regards,

    Hooman

  • Hi Moha,

    I'm beginning to think that there is something inherently unstable with your Stage 3 which may or may not explain the 1.67kHz instability you are getting.

    Essentially, it comes down to the issue of phase shift around the loop approaching 180 deg. when your loop gain is 0dB. A differentiator circuit, when built with a voltage feedback amplifier is inherently unstable and needs to be compensated for stability. The same mechanism is at work here with the LMH6702 current feedback amplifier due to the feedback resistor (390ohm) looking at the input capacitor (33pF) which causes additional phase shift around the loop.

    Considering the loop gain analysis in this application note (link below), I've used TINA-TI to demonstrate that if the input capacitor is large enough, Stage 3 will not have enough phase margin.

    http://www.ti.com/litv/pdf/snoa366b

    The exact operating point of your circuit does not show any simulated instability, but increasing Cin will eventually show instability in simulation.

    Here is your circuit conditions which shows a phase margin of 43 deg. (low but probably not enough to oscillate blatantly (assumed Ri= 20ohm- no value in the datasheet):

    Phase Margin with your conditions:

    Here is the simulated phase margin with various Cin:

    Cin                              Phase Margin

    33pF                           43deg.

    100pF                         27deg.

    1000pF                       15deg.

    It seems like a practical way to remedy your situation is the same as item 5 in my previous post (Resistor in series with Stage 3 Inverting input) where adding 100ohm in series with the inverting input improves the phase margin to about 62 deg. (which is adequate. Of course this is simulation and should be bench verified as well.)

    Improved stability with increased Ri (100ohm added in series with inverting input- schematic does not show value as increased Ri is factored in the Post Processor waveform for "Stability" plot instead):

    I did not test this, but it seems like a small value capacitor across RF would also work to reduce phase shift around the loop and help your cause (however, be careful as current feedback amplifiers do not like to see a pure cap across feedback).

    Here is the TINA-TI file I've used (in this case, I've assumed Ri to be 120ohm which is 100ohm higher than the image further up to demonstrate the increased phase margin by adding a resistor in series with the inverting input).

    3302.LMH6702 cap input open loop analysis increased Ri E2E Hooman 10_24_14.TSC

    Regards,

    Hooman