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Original question:

OPA2810: most JFET input voltage & most positive input voltage

OPA2810: most JFET input voltage & most positive input voltage and some specs

Lacey Lin
Intellectual 2900 points
Part Number: OPA2810

Hi team,

For the input voltage, you have mention in other post that in the JEFE input stage, the performance will degrade.

1. Can you help to describe which specs will degrade?

2. For the common-mode input voltage, the range is from (Vs-)-0.3 to (Vs+)+0.3 or (Vs-)-0.3 to (Vs+)-3?

3. in addition, I see the Absolute Maximum Rating, the input voltage range is Vs- to Vs+. It's within the (Vs-)-0.3 to (Vs+)+0.3(above table). So I am confused with this two specs. Please help to clarify the relationship.

Another question is about the output short current.

4. For the Io_max, is it test when we set the load as 1Kohm, and the maximum current we can get. Does it also show the maximum output voltage?

5. For the Isc, what's our test method? Do we put the output to GND and test the current?

So many questions, please help to look at them!

Lacey

Thanks a lot！

  • 0
    Guru 140200 points
    Hi Lacey,

    1. To which post do you refer?

    2. This is explained in section 7.2.

    3. Do you have the latest datasheet of OPA2810? In my datasheet from 2018 the maximum input voltage is Vs- -0.5V to Vs+ + 0.5V.

    4. Yes, it's specified in the datasheet. Have a look at the bottom of page 6.

    5. Yes, the output is grounded. Have a look at figure 17 of datasheet.

    Kai
  • 0 in reply to kai klaas69
    TI__Intellectual 2900 points
    Hi Kai,
    Thanks a lot for your reply!
    1. the post address is
    e2e.ti.com/.../625148
    2. I have read the section 7.2 in the latest version 2018, but I still can find the range for the input common mode. I suppose the common mode voltage range refer to the most positive input voltage and most negative input voltage. is it correct?
    3. I am not refer to the lasted version, sorry for this.

    Lacey
    Thanks a lot!
  • 0 in reply to Lacey Lin
    Guru 140200 points
    Hi Lacey,

    1. Ah, ok. Input offset voltage, for instance, is degraded when the input stage switches between the JFET- and the CMOS-circuitry. Have a look at figure 18 and figure 35 of datasheet.

    2. You destroy the chip when the input voltage is more than 0.5V beyond the rails and the input current isn't limited to under 10mA. The OPAmp will "work", even without phase reversal, if the input voltage is no more than 0.2V beyond the rails. But the performance will be degraded. And the best performance is achieved, if the input voltage is more than 3V below the positive rail.

    Kai
  • 0 in reply to Lacey Lin
    TI__Genius 14036 points
    Hi Lacey,

    Amplifiers operating close to the edge of their input CMVR will have decreased linearity as the input transistor begins to saturate and clip. The absolute maximum input range for this device is 0.5V beyond each rail, as this is a JFET input device. Thank you Kai for your continued assistance.

    Best regards,

    Sean