I believe the circuit below is what you are describing... correct?
There is more subtlety in this circuit than you might imagine.
This circuit has a gain of -R2/R1 = -1. C1 working with R1 roll off the response at approximately 160kHz. Closing the feedback loop after R3 allows the amplifier to correct for any voltage drop in R3 in driving the load. R3 and C2 form what we sometimes call a "flywheel" driver for the ADC. This circuit allows C2 (just a wild guess of its value) to absorb the current glitches or pulses that are often produced by the input of the ADC. The whole circuit would typically be optimized for the particular combination of op amp and ADC to produce the best results for settling time or other dynamic behaviors. Sometimes the feedback loop is closed on the other side of R3.
Hope this helps, Bruce.
R2 and C1 are chosen according to the required bandwidth. If bandwidth must be limited then capacitor values will become larger. It sounds like you are describing the series resistance and inductance of electrolytic capacitors. These would not be a good choice. Polycarbonate capacitors would be good in the 1uF range. Thee are many factors that could come into play when selecting a high value capacitor for very critical applications. Often, mylar types are adequate.
Optimum values for R3 and C2 are very dependent on the op amp and data converter.
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