The gain calculation shown on page 14 of the datasheet--an application circuit--shows that the INA333 has a gain of 10. I'm assuming that this value is derived from the RLD drive circuit, in series with the RG resistors 2.8K. The combined resistance is 11.4K, which results in a gain close to 10. Is this correct? Otherwise, how do you come up with the gain calculation.
Also, can you provide a sample input circuit for the bias current return path? This would be for an ECG application.
The gain of 10 is not in agreement with the resistor values shown. The resistor values shown will produce a gain of approximately 19. The right-leg drive circuit does not affect the signal path gain.
I'm quite certain this is a cut and paste error, copied from another INA data sheet. Many of our other INAs have two internal 25k resistors on the input stage and this works out to be a gain of 10 for these other devices.
Thanks for the response. I'm running into a problem using the INA333. My simulations work just fine, but when I do board testing, the gains vary dramatically. I'm attaching a copy of the circuit for an ECG application. Feel free to review the circuit yourself with the parameters below (see parameters).
To summarize, in my application I'm using the INA333AIDGKR, I'm using a similar circuit to that which is shown on page 14 of the datasheet with two notable exceptions. First, I don't use the RLD drive circuit. Second, I drive the reference pin to 625mV using an op-amp (OPA349NA/250) in buffer mode.
Under this scenario with an Rg of 100K, the gain is ~1.3x instead of 2x and with an Rg of 10K, the gain is ~1.8x instead of 11x. When there is no Rg, the gain is 1x as stated in the datasheet.
I just don't understand why I'm seeing this behavior across a number of my pre-production boards. Can you help troubleshoot my problem?
VANA = 2.5VVMID = 0.625VGain = 1.8 with Rg (R3) = 10K
I've attached my .jpg file and the TINA circuit file.
I don't see your TINA file attached. Our E2E forum has some issues going on in the last week and this may be why. Check whether you can see your file attached to your posting. If not, please try again.
My guess, from the information supplied, is that you are not operating one of the input amplifiers in a linear range. This is tricky business with an INA. The input terminals may be within the range of the op amp (rail-to-rail with this design) but the input conditions cause the output of one or both of the input amplifiers to hit the rail. You can't measure these internal nodes so you must infer what these voltages should be from the two input voltages and gain.
My guess is that one of the input amps is hitting the rail and one is not. The result is an apparent gain error. Try measuring with a small differential input signal and a common-mode voltage halfway between the rails.
I'm reattaching my TINA file and the picture file of my circuit.
One more thing. The leads from the ECG connect to the IN-AMP as shown in the TINA file. The frontend is biased at 625mV, which is within the limits of the VCM of the part. Can you clarify your point about the type of "input conditions" that would rail the amplifier? I'm going to try to measure this sometime tomorrow. Please let me know of any other tests I should perform while I'm in the lab.
I believe that your biasing approach may be putting you on the lower edge of the common-mode range of the INA333. See the discussion in the data sheet on input common-mode range--page 13. Can you try increasing the Vref voltage to 1.2V or so, as a test? Make this change to both the input and Ref terminal offset. See if it behaves more normally. I'm also a bit concerned about using the OPA349 as a buffer for this node. It is a nano-power amp that has very high open-loop output resistance and may have difficulty holding this node solid. Check it out and see if it is moving significantly under signal conditions.
Another point: You have voltage dividers that attenuate your input to about 95% of input value. Be sure to account for 5% loss in gain. The high impedance of these dividers adds significantly to the noise of your circuit. Resistor tolerance of 1% will degrade the common-mode rejection.
I will check the circuit tomorrow. In the meantime, regarding your advice about the OPA349, when you say the output resistance is high (open loop), is this because the drive stage is a CLASS A-B FET? Isn't this nullified becasue of the feedback. In other words, the output resistance is decreased by the loop gain. I guess I don't see how this relates here.
I did a quick simulation and found that the output impedance of the OPA349 is approximately 100 ohms at 150 Hz and rises linearly with frequency. This is not quite as high as I thought and may not be an issue. You are correct that open loop gain reduces the output Z but the modest bandwidth of the OPA349 means that you don't have so much gain at high frequency.
The open-loop output impedance of a rail-to-rail output stage is high because the high impedance of the drains of the output FETs.
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