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24 bits ADC and analogue front end designV
I'm attempting to design a analogue front end with 24 bits ADC with low leakage op-amp (for 1Meg termination at the I/P), similar to scope.
I have +/-5V PSU and would like to have +/-4.5V I/P signal with low bias i/p op-amp but most JFET have limited I/P voltage range (ie not rail to rail input).
The +/-4.5V is then translated into 0V to 5V (or 4.5V) into the ADC. I have 2.5V precision reference.
The input is differential or single ended (by shorting the -VE to GND.
The offset can be removed by calibration (by software) but not the drift.
Can anyone link me to schematic example based on above recommends instrument op-amp or op-amp that is suitable for this task.
I aim for 16-18 bits resolution.
PS I forget to add....the 1Meg is for x10 probe. However it can be reduced to 10K for lower noise as required for higher resolution
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