INA219: Register handling and conversion

Hello Florian,

Thank you for considering the INA219 for your design.  I am looking into your questions and will get back with you.

Hi Pete,

thanks for your extensive answers.

Pete Semig

3)  Again datsheet page 15: "...INA219 can be read at any time, and the data from the last conversion remain available..."

Shunt voltage and bus voltage are converted at different times.

Are the shunt voltage register and the bus voltage register (and the depending registers)  updated at the same time?

Or is the shunt voltage register updated (and current register and power register) updated after the shunt voltage conversion is finished?

The output registers (shunt voltage, bus voltage, current, and power) will retain their values until the ongoing conversion is complete.  As soon as the ongoing conversion is complete the new values for the output registers will be loaded and CNVR will go high.

If the conversions and calculations are finished (and the conversion ready bit is set) may I start a new conversion without overwrite the actual register values?

Yes you may start a new conversion.  The data in the output registers will not be overwritten until the new (or ongoing) conversion is completed.

I think the INA219 needs 2 conversions, the shunt voltage and the bus voltage.

Are the output registers stable until both conversions are completed? Or is the shunt voltage register updated after the shunt voltage conversion si finished?

The power register depends on the shunt voltage (via the current register) and the bus voltage register. Is it updated twice?

Thanks a lot for your help

Florian

Hi Pete,

Pete Semig

Hello Florian,

I believe the confusion stems from the term 'conversion'.

Perhaps a better way to think of this is in terms of a 'cycle'.  Let's use the term 'cycle' to represent the total time it take for shunt conversion, bus conversion, calculations, and register loading.  With the term 'cycle' defined we can state the following:  the output registers will retain their values until the cycle is completed. The INA219 datasheet uses the term 'conversion' to represent a complete measurement and calculation cycle.

The cycle term is a very good idea.

In chapter Basic ADC Functions the datasheet decribe a shunt voltage conversion and a bus voltage conversion. That is the reason for the confusion.

Ok, but now another question about conversion:

Is the converion time in Tabe 6 (ADC Settings) for every ADC conversion?

I assume if I use the Configuration Register default settings I need 1064 us (internal, without communication) for one cycle. Correct?

Thanks a lot.

Best regards

Florian

Hi Pete,

thanks a lot for your help and your patience.

Best regards

Florian

Hi Sir,

    Why such lower the conversion time? It's around just 2kHz BW (1/532us). This INA219 front end ADC sampling rate is 500kHz, but conversion time drives BW down to just 2KHz. it's 250 times lower than sampling rate. if so, it seems it's hard to be used on current monitor purpose where current to be measured contains frequency components higher than 1kHz.

Hi Rong,

You're correct, the INA219 is not the correct choice for applications interested in current measurements at frequencies greater than 1kHz.  The ADC in the INA219 is a delta-sigma converter which is an over-sampling type of data converter.  A one-bit ADC produces a high-speed data stream at 500kHz that is then low-pass filtered and averaged to get the final conversion value.  Increasing the conversion time increases the resolution because you basically average more data points together for the final answer. 

Since all of our digital-output current-shunt devices use a similar converter architecture you will have to look into another type of output to perform this higher bandwidth measurement.  My recommendation would be to consider an analog output type of device such as the INA21X or INA27X family of devices which have bandwidths up to 130kHz and then use one of TI's SAR converters to accurately digitize the analog signal.  

Regards,
Collin Wells

Thank you ver much Collin, very clear. Here I have another question to consult.

As you TI's saying in previouse replying, "the output registers will retain their values until the cycle is completed". It sounds to me that the sampling rate will be down to 1/532us, so that, a 1kHz antialiasing filter must be designed in front of ADC input. This would result in breaking the intrinsic advantage of sigma-delta ADC nature, oversampling so as input antialiasing filter free (or smaller). Is it correct?

Regards,

Rong Lin

Hi Rong,

The anti-aliasing filter for lower frequency signals such as 1kHz is handled by the SINC filter built into the sigma-delta, you can see it's effects in the frequency response graph (Figure 1).  So you're correct, sigma-delta converters should not need a low-frequncy anit-aliasing filter.  However, as mentioned in the "Filtering and Input Considerations" section if you have any higher frequency signals in your system then an external anti-aliasing filter is suggested and should be implemented as shown in Figure 20.

Regards,
Collin Wells
Precision Linear Applications 

Hi Collin,

    Thank you! So, the 532us conversion time (cycle time or output register reflash time) doesn't affect sampling rate. The sampling rate is still at 500KHz speed, but output register reflash rate is just 1/532us (it's not equal to sampling rate down to 1/532us). No aliasing issue happened. ^___^!

Regards,

Rong Lin