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Pin 1 on TLV3011 SOT-23-6?
I cannot identify pin 1 on the TLV3011 SOT-23-6 device with 100% certainty.
My prototype simple battery over-voltage protection circuit with hysteresis using the tlv3011 simply refuses to work. Maybe I have misidentified pin 1 on the package.
The data sheet shows a chamfered area at the corner of the package rectangle that identifies pin 1. However, the delivered device has no such chamfering. Printed on top of the device is "ALR". I chose pin 1 as being near the first leg of the "A". MAYBE there is a small divit in the opposite corner to identify pin 1. Maybe my loupe is not strong enough. Should there be a divit and I just can not see it?
Pin behavior behaves SOMEWHAT correctly (default position Vref pin is at 1.248) volts, but still, the simple circuit (based on the data sheet "Battery Good" circuit) absolutely refuses to operate correctly. I am very confused.
Silly, I know. But can someone please help me find this. The next step, if I was correct in finding pin 1, is to post the circuit and ask for help.
Thank you, in advance.
Sorry you're having problems. Slight variations in package vendors can make identification of orientation tricky. Sounds like you've got it correct if you are getting a solid reference voltage.
Are you applying the Vref directly to one of the inputs? What is your supply voltage? The TLV3011 requires pull-up on the output... do you have one connected?
Thank you, Bruce,
I've got a 100k pullup on the output. I'll send a .jpg (see attached) of the schematic if you or other would be so kind as to comment. IC3 in schematic is TLV3011, R7 is pullup, B1 is battery, high impedence source (solar) is on left at J3. IC 2 is simple switch TI TPS27081 turn on with jumper betw pins 1 and 2 of connector J2. other resistors are primarily hysteresis trigger point for TLV3011. At trigger voltage, Q1 P-Ch mosfet gate should go LOW turning on FET and stopping charging of Batt.All Jumper test points are closed.
Board is powered from high impedance source to slowly charge a (tested good) battery , so voltage ramp up of charge from near 0V is relatively slow, but easily exceeds min operating voltage of 1.8V for the chip. Problem is that circuit is intended to shut off current past set/configured voltage (with hysteresis) but circuit never turns off the charging (never turns on the overflow p-channel fet at the set trigger voltage).
Let us assume that the schematic is correct for a moment. If it is not, please throw a rock at me and tell me where I am wrong.
I soldered prototype with "skillet reflow" method. Using an IR temperature gun, board got to about 225 deg. C and turned off skillet power (I did NOT remove board immediately). Maybe board stayed at 225 deg C temp too long?
The data sheet shows an abs max junction temp of 150 deg. C. Could reflow have broken this (on multiple boards)? It would seem that a production reflow heat profile would exceed 150 deg. C junction for this device, suggesting that the device would be hard to break with skillet reflow.
Of course I am being very careful with ESD (wrist strap, ESD Pad, etc). This is killin' me.
Thanks for any replies.
I understand the basic idea of your circuit but I believe you have a fundamental flaw. When the comparator output goes low it pulls the gate low. The source of T1 falls slightly but loses drive as the source drops in voltage. It is a source-follower circuit and it has no gain. The gate cannot go low enough to fully pull the source fully to ground as I think you want.
I believe you need to use an N-channel FET and reverse the polarity of the comparator drive.
In my previous post I referred to T1. I should have called it Q1. And I should have added a couple of other comments:
If the output of the TLV3011 goes low at the expected voltage, it is doing all it can to shut off Q1. This would be an indication that the issue is with the source-follower configuration of Q1.
I think it is unlikely that you caused damage during your soldering operation. If you have a proper reference voltage and the output of the comparator is toggling at the expected voltage, all is good with the TLV3011.
Thanks Bruce, Holidays here so had to get other things done before responding ...
I don't see your point WRT the follower circuit. My physics training is weak in electronics. Still, are you certain of your interpretation of the follower?
Attached is image of similar TINA simulated circuit for the purpose of our discussion. Circuit was originally designed by third party to use with their device. Also attached is a graph of the transient of the simulated circuit starting with all nodes at zero V.
The simulation suggests the circuit should work. I don't know what the "glitches" are (maybe spice model artifacts or other?).
It seems that as Vout reaches threshold, the output of the TLV3011 goes to ground thus turning ON the p-chan xsistor. If the source-drain Voltage goes to zero as a result, the current source will pump up C2 thus biasing Src-Drn to conduct, and putting desired polarity voltage on gate-source. Again, xsistor conducts, as desired.
On another tack, I did, in fact re-measure the voltage at the inverting input of the comparator. With Vout at 3 Volts, V at the inverting input (midpoint of the voltage divider) was 0.6 volts DC. (then I accidentially fried the circuit while testing ... again). The former facts enable the calculattion of a DC input impedance of the inverting input of approx. 400k ohms ... 8 orders of magnitude below the spec! This is consistent with what I think I have been seeing, and maybe (?) becomes apparent when using such large resistors for the purpose of low power consumption.
I appreciate your feedback and or corrections. Otherwise I do not understand the circuit and/or suspect issues with the TLV3011 actual input impedance. Or maybe I damaged the chip. I don't know if I can be much more careful physically handling the device after several tries now.
Looking forward to your response.
Oh. The "glitch" would seem to be the sudden discharge of C2 upon turning on the xsistor.
The operation of your circuit will depend greatly on the characteristics of the MOSFET you use. The device type in your latest simulation circuit has a max threshold voltage of 2V at 1mA. In your circuit this means that when the gate is at 0V, the source can be pulled down to 2V when sinking 1mA. This is a low threshold voltage device so that's pretty good but it may not be good enough. Not sure if this is the actual FET you used. Temperature variation of threshold voltage could change the performance. Using a common-source connection of an N-channel device would make this a much more robust design.
I'm not sure about your simulation as results will depend on the characteristics of the MOSFET model you use. Interesting that the simulation shows a proper reference voltage output even when the supply voltage is less than the reference voltage. This is a problem with the macro model as the device clearly cannot do this.
Regarding your measurement of the voltage on the resistor divider. What is measurement method? A 1M-ohm scope input will severely load this network with 1M resistors. You never provided resistor values for your original circuit so I'm not sure what you've got there. A properly operating TLV3011 will not load this node significantly
Hi Bruce, I hope you have had a good week.
The chosen mosfet for my circuit is IRLML6401, which has parameters well beyond what is necessary to allow this circuit operate properly (Vgs-thresh =-0.55 V @ 250uA)
see data sheet: http://www.irf.com/product-info/datasheets/data/irlml6401.pdf
The transistor and circuit behave properly when the xsistor gate is driven manually to ground. The temperature is 25 deg. C, +- 4 deg. I do not see a problem with the transistor.
The problem seems to be that the TLV3011 does not want to allow the input at the inverting input voltage divider to rise to the comparator theoretical trigger point.
Yes, simulations are far from perfect. However (and if memory serves me), I was SURPRISED to measure a reference voltage ABOVE the input AND output BEFORE the circuit was fully "charged." Again, I am not an EE, and guessed that it might be a transient state that a current mirror, internal to the chip, might be going through on the way to reaching stability?!#
The input impedence of my probe is > 10 M-Ohm, so I don't see a problem there (I have allowed the output voltage to go well above the trigger point).
Other important parameters of my circuit (the attached schematic with black background) are:
R1 = 2.7M (1% tol)
R4 = 2.37M (1% tol)
R5 = 86k6
R6 = 10M
Yes, big resistors for low, low, power. However, small compared to specified impedances of the TLV3011.
It seems we might be beating around the bush. I still suspect one of:
1) A problem with the simple design of the circuit (different from your suggestion of insufficient mosfet drive)
2) An issue/problem with the actual performance of the TLV3011 compared to spec
3) Parts damage (ESD, overheat, etc), though I have carefully built this circuit multiple times.
4) Transient instability of the chip as it moves slowly to its operating point?
5) Something other that I just don't understand
It is expensive in time to try other circuit configurations (e.g. n-channel mosfet) and money as a PCB has been fabricated for the current circuit. It also seems a bit arbitrary to just "try" an n-channel FET. Also, the circuit, as designed, seems as though it should be good/fine under the given operation conditions. I would expect similar problems if I was to re-create the circuit with an n-channel FET.
I would really appreciate a stronger analysis of the problem, if possible. I am stuck on my problem with the TLV3011 and it is costing me, greatly.
Thank you for your help.
Okay, got it. You've got a very low threshold FET so tho output circuit should be okay. Grounding the gate, as you did, is a good test of what the TLV3011 should be able to do. For the record, what is the value of R7?
If you have verified that the voltage on the inverting input is not rising to the trip point then that is the issue to address. It's difficult to imagine a fundamental behavior of this input that would cause this. My best guess would be some type of damage to the device or contamination of the board during the soldering operation.
As a diagnostic, try driving the inverting input node with an external voltage source (a lower impedance) to see if you can get the comparator to trip. Have you tried replacing the TLV3011? That's the next step.
Thank you for the quick response, Bruce.
R7 is 100k.
I have to re-verify the issue of the inverting input's failure to rise as expected after rebuilding the circuit. I have run out of exact parts and have to use a different Schottky but I don't think that will be a problem.
I inspected for board contamination - no visible problems. Device damage could still be the issue though I have tried hard not to allow this. This is a well-established IC, yes? Especially for a DC app such as under discussion (I would expect significant use of the chip as an ADC reference where DC ... super-low freq ... impedance might not be as important/apparent). I would appreciate any knowledge of the maturity of this chip in any similar app.
I agree that the most probable cause is IC damage, but it will be hard for me to be more careful.
I will get back to you after rebuild/retest. However, I am much better at theory than at lab work, soldering, etc.
(should we continue this discussion offline?)
The TLV3011 is well-established. It's had a few quirky issues through the years but I don't think they relate in any way to what you're seeing. It's rarely used as an ADC reference. It's more likely used the way you do, including high resistance components for low power. I don't expect that the slowly changing supply voltage is an issue. I don't see a bypass cap on the supply in your circuit. I think that would be good practice, though the battery impedance is probably low enough. I know better than to assure you that it can't be due to the basic behavior of the part, but I still think it's unlikely.
Sounds like you are probing with a scope. Look for oscillations or other weirdness, including on the reference pin.
We can continue on the forum unless you are uncomfortable with it.
Another thought: It is showing some symptoms of a disconnected V+ pin. The reference circuitry could be powered from the voltage applied to the inverting input pin flowing through the internal protection clamp diode. This might allow the reference to appear normal while the comparator fails to operate.
Hi Bruce, thanks for hangin' with me ...
OK, so I had 2 tlv3011 chips left (Thank you, TI, for samples).
Just because I am now becoming superstitious, I put one chip in "backwards" to be sure I got pin 1 identified. We had pin 1 identified correctly from the get go. Pin 1 is at the lower-left leg of the "A" in the "ALR" marking. That is, the "backward" test showed it was all wrong.
So I put other tlv back in, forward direction (lower-left leg of "A" is pin 1). fixed a solder bridge (a few years of age and SOT-23 pin pitch do not mix well). I get my 1.244 ref voltage out of the ref pin (good). I checked V+, it is correctly pinned to the target supply/batt voltage (2.7 V). However, I still get 0.56x volts at IN- (same node/potential as common side of R1 and R4. Checked my smt resistors (visual read of values ... correct). Current is sneaking out from that node somehow (IN- node).
Yes, I have a low ESR bypass cap (batt is actually cap ... bit proprietary).
Unfortunately, no scope here. Using a pretty low level fluke dmm.
I'll see if I can get some Hz reading or significant rms power reading on the board (theoretically all AC should be quiet).
I agree, probability, Murphy's law, (and its corollary - the embarrassment law) suggest the TLV3011 is probably NOT at fault. It is probably implementation (bad solder) or bad circuit (somehow?). However, like you I cannot rule out the chip input impedance being lower than spec'd. I also keep building this and similar circuit to same end result.
Was thinking of moving high side of both R7 and Q1 to other side of diode D1. Theoretically, I don't think this should matter when driven by current source, however, and I think would be exercising superstition. It would cost a little bit in the way of leakage power and time and energy. Also, not enough schmart boards or adapters to put SMD's onto 0.1" breadboard. I'd rather understand just what the heck is happening.
I will look for other paths on the board that current can get from IN- to ground. There don't seem to be many except through the TLV chip. In the meantime, if you have a line to the design engineers and might be able to ask them if it is crazy what I see on pin "IN-" (like does it ever have lower impedance than expected) that would be soooooo nice.
Bruce, simply reciting your short list of possible causes (incl. contamination) made me clean the board again. After very tedious and careful cleaning, heating the board to 85 deg. C for a while, the voltage in question (IN-, or voltage divider) near doubled. AHA! Still Cleaning and checking, but things look better (not solved, but maybe). I am not used to SMT (older stuff and little of it) and was not ready for board surface conductivity with such a high impedence/low current board.
My PCB layout for the TLV3011 (.png file attached) had a trace passing under the small SOT-23 chip. I think maybe some flux residue under the chip, combined with the nearness of conductors, allowed leakage current between pins that was comparable to design parameters.
I'll send another update, but I think the take-away, at a minimum, is:
1) Use more care in circuit layout for high impedance parts. (incl., maybe guards)
2) Cleanliness is next to ... well, you know who
3) It is usually your (my) fault
3) the corollary to Murphy's law is again verified in the wild.
I'll probably have to start with a virgin board and rebuild, with much attention to cleanliness. I might even have to create a new layout.
You are awesome, Bruce
I'll post a final, soon (assuming that all observations fit our hypothesis and the board behaves as predicted).
(note traces near high impedence inputs on SOT-23-6)
Looks like you are homing in on the problem. A very minor layout change could eliminate some vulnerability. The blue trace shown below would avoid some possible leakage under the IC. Don't know whether the other trace could be as easily re-routed. Many layout folks go to great lengths to avoid traces under a surface-mount IC, even when impedances are low. Even aggressive production cleaning processes can leave some gunk under ICs.
For a discussion of some unrelated PCB layout issues with some helpful links, see this blog:
BTW... I accidentally checked the box indicating that the question was answered (too much wine). Feel free to un-check it.
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