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AFE032 Clock requirements

Other Parts Discussed in Thread: AFE032

Hi,


I intend to use the AFE032 in the FCC band with a sampling frequency of 1.2 MHz.

The ARM processor interfaced with the AFE032 runs at 168MHz and can generate signals that are divisions of this.

So, the processor cannot exactly generate 19.2 MHz, which can be divided by 4 for DAC_CLK to be 4.8MHz.

What are my other options here?

Regards,

Karthikeyan

  • Hello Karthikeyan,

    You have many options and reading the “SPI Clock To DAC Clock Synchronization” section of the AFE032 datasheet (pag. 30 to 32) gives a more complete explanation.

    One particular option you have is to divide the 168 MHz clock from your processor by 6 and feed a 28 MHz signal into the XCLK pin of the AFE032 (pin 10). Then you can choose a divider (see “AFE032 Clock Requirements”, pag. 25 of the AFE032 datasheet) of 5 and that will yield a DAC_CLK signal running at 5.6 MHz. Then, you would enable Block 3 and Block 4 of the DSP path and calculate the Block 4 parameter as described in pag. 32. The resulting parameter is 0x00DB6DB6DB and it should be written onto register addresses 0x10 through 0x13 as indicated on page 37,  49 and 50.

    Hope this helps.

    Best regards,

    Jose

  • Thank you for the response Jose.

    I have revised my application to work with a sampling frequency of 400kHz, utilizing the FCC_LOW band (35 kHz to 148 kHz).

    I have tried to generate XCLK in the higher ranges, but unfortunately could not generate a clean clock signal. There seems to be more than desirable capacitance on the signal line and the maximum clean clock signal I can generate is ~ 10MHz.

    So I chose an XCLK of 8 MHz, divide by 5 by writing 4 to DAC_PRECLK_DIV in REG_CLK_DIV register.
     Now DAC_CLK = 1.6 MHz, which is 4 times the sampling frequency.

    I included Block 3, as suggested in the datasheet.

    Should the duty cycle of the XCLK signal be precisely 50%. I am able to generate 8 MHz, 52%.

    What's your take on this? Will this work fine?

    Regards,

    Karthikeyan

  • Hello Karthikeyan,

    Yes, the configuration you mention should be fine and 52% duty cycle is OK. Please see you other forum post for the complete answer.

    Best,

    Jose