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AFE032 DAC Digital Filtering configuration

Other Parts Discussed in Thread: AFE031, AFE032

Hi,

The datasheet talks about digital filtering for three bands - CENELEC_A, ARIB and FCC bands.

What configuration needs to be adopted for an application working in all CENELEC bands (A,B,C,D): 35 kHz to 148 kHz with a sampling frequency of 400kHz.

Also, page 31 of the datasheet doesn't mention about which blocks of the DSP path needs to be enabled for a sampling frequency of 400 kSPS.

Please comment on using XCLK frequency of 8MHz. This is the frequency that could be generated by the application processor I use, closely matching the jitter requirements. Does the XCLK need to have exactly 50 percent duty cycle?

What do the default values of the coefficient registers of the Digital filtering blocks signify?

Regards,

Karthikeyan

  • Hello Karthikeyan,

    The ARIB band configuration would be the best option to use if you are interested in transmitting in the CENEL A, B, C and D band. Note also that you have the option of using the AFE031 if you are not planning to upgrade your product to higher frequency bands in the future. The AFE031 does not require an XCLK signal.

    If you are using an 8 MHz for XCLK and send DAC samples at 400 KSPS, then you should include Block 3 and bypass Block 4.

    The XCLK should be as close as possible to 50 % duty cycle. In no event however, should either portion of the clock signal (high portion or low portion) last less than 12.5 ns.

    The default values of the coefficient registers for the digital filtering block correspond to the necessary values for specific applications. For example, the default bits in registers 0x10, 0x11, 0x12 and 0x13 correspond to the case when Block 3 is bypassed, Block 4 is used and clock divider is set to 45 as indicated on table 11 of the AFE032 datasheet.

    Hope this helps.

    Best regards,

    Jose