Hi,
The datasheet talks about digital filtering for three bands - CENELEC_A, ARIB and FCC bands.
What configuration needs to be adopted for an application working in all CENELEC bands (A,B,C,D): 35 kHz to 148 kHz with a sampling frequency of 400kHz.
Also, page 31 of the datasheet doesn't mention about which blocks of the DSP path needs to be enabled for a sampling frequency of 400 kSPS.
Please comment on using XCLK frequency of 8MHz. This is the frequency that could be generated by the application processor I use, closely matching the jitter requirements. Does the XCLK need to have exactly 50 percent duty cycle?
What do the default values of the coefficient registers of the Digital filtering blocks signify?
Regards,
Karthikeyan