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dudas con AFE031

Other Parts Discussed in Thread: AFE031

estimated

could help me with the following questions that I have about AFE031.

setting the AFE031 in two-wire mode and connecting directly E_Rx_OUT E_Tx_IN and Tx / Rx USART of MCU. Is it possible to establish an asynchronous serial communication (baud rate 19200)?

the output levels of the PGA of E_Rx_Out can be configured as CMOS outputs?

take as a reference page 33 and 34 of the datasheet

thank you very much for your support!

best regards

Cesar Zicker...

  • Hello Cesar Zicker,

    Perhaps I am not understanding your question correctly. The AFE031 cannot be programmed using the ETx and ERx blocks. The ETx and ERx blocks are intended to allow for the transmission of on-off keyed signals onto an additional and independent pair of wires.

    There are applications where it is necessary to establish two communication links, one over the power line (using the Tx path in conjunction with the PA nad Rx path) and another over a secondary pair of wires (using the ETx and ERx blocks.)

    Let me know if I misunderstood your question or if I can clarify the use of the ETx and ERx blocks.

    Best regards,

    Jose

  • Hello Jose

    thanks for your response!

    I apologize, I think I have not expressed well, my question is, if you can establish a serial asynchronous communication between two MCU's in the way shown in the figure using the USART module of the MCU's for it.

    5488.af.pdf

    and if so, output Rx_PGA2_OUT that would connect with the RX USART module input would be giving me a CMOS level?

    Best Regards

    Cesar Zicker

  • Hello Cesar Zicker,

    It is not possible to establish a connection between two MCUs as you showed in the document attached to your previous post. The data put into the E_Tx_In pin is modulated by the E_Tx_CLK signal and the result is put out in the E_Tx_Out pin; such data never makes it out directly to the PA_Out pins; you would have to connect the E_Tx_Out to the PA_In via a capacitor in order to observe the signal in the PA_Out pins.

    Hope this helps. Best regards,

    Jose

  • 0728.tra_afe.pdfThanks Jose, it is clear to me, then for mode Two-wire connection of stages would be correct as listed in the attached PDF?

    Thanks for your help

    best regards

  • Hello Cesar Zicker,

    I have a question about the frenquency of SPI in AFE031.

    I have set the 031 DAC mode.And set the SCLK in SPI 20MHz..I want to sent 12  points (sent a 16 bits binary represent a point) to simulate a 150KHz sine wave,but  the frenquency can't up to 50KHz, and the extreme frenquency is 20MHz/16 bits/12 points=104KHz..Is the frenquency of 150KHz beyond the range of FAE031?

    Or the derivation above has some wrong?

    Thank you !

  • Hola Juan

    La frecuencia de muestreo del DAC es 1,5 MSPS
    Por lo tanto los anchos de banda de los bloques de TX, RX y PA como la tasa de muestreo de la DAC aceptan los parámetros que usted propone. pero no cumpliría con las normas CENELEC también
    usted debe volver a calcular los valores de los acoplamientos.

    atentamente

    Cesar Zicker

  • Hello Juan

    The sampling rate of the DAC is 1.5 MSPS
    Therefore I bandwidths of the TX, Rx and PA blocks as the sampling rate of the DAC accept the parameters you propose. but would not meet the CENELEC standards also
    you should recalculate the values ​​of the couplings.

    Best Regards

    Cesar Zicker

  • Hello Juan

    The sampling rate of the DAC is 1.5 MSPS
    Therefore I bandwidths of the TX, Rx and PA blocks as the sampling rate of the DAC accept the parameters you propose. but would not meet the CENELEC standards also
    you should recalculate the values ​​of the couplings.

    Best Regards

    Cesar Zicker

  • Hello Cesar Zicker,

    Thank you for your answers,but I also have some questions .

    How can I only pass 10-bit binary data into the AFE031 DAC? If I pass 8-bit binary (1110,1011) , the valid data in the DAC register is 00,1110,1011 or  1110,1011,00,or something else? Can I only send 8-bit binary data into the AFE031 DAC?

    Thanks!

  • Data is left justified, if you send the following 8 bit data 11101011 as offer the DAC will be 1,110,101,100.
    note that the DAC is a check-in series, if the data is moved to the right and only you send 8 bit, the data occupying the bit 8 pass to take the bit 0 in the new data, ie if DAC have the data you send 1100111100 and the following new single 8 bit data 11000000, the new data in the DAC will: 1100000011 the bit 8 and 9 of the previous data to pass to fill bits 0 and 1 of the new data.

    should be ever so anyway probe in practice this ...


    regards

  • Thank you for your patience.But I can't always receive the right ADC data.If I send 0xff,the PIN14 of AFE031 is 3.2V,send 0x3f ,the receive is 2.6V,send 0x3c,the receive is 0.2V,send 0xfc,the receive is 0.8V.Would you explain this ?

    Thanks again for your answer.

  • the MSB bit is justified to the left means that the data is inverted in order, check the SPI module of the MCU, the option of sending data, they have the option to transfer data information to the left or right, some MCU's is the UCMSB bit ....

  • Correction: the LSB bit is left justified ....