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TLE2141: Scaling and biasing a.c. signal for ADC input

Part Number: TLE2141
Other Parts Discussed in Thread: TLC2272, REF2033, OPA196

I have to condition a low frequency (1Hz - 150Hz) signal that fluctuates within 3.5V max above and below signal ground. The purpose of the conditioning is to convert the signal to 0 to 3.3V so that it may be read by the ADC on my microcontroller. My power supply rails are +/-5V split.

I have two problems: (a) Make sure that the signal to the ADC has the maximum dynamic range of 0 to 3.3V but doesn't go outside the 'no damage' range -0.5V to 5.0V; (b) offset the signal so that I can adjust the zero input level to be 1.65V.

I have shown my attempted solution below. This must be a common problem so I'm wondering if there's a better way to do it? In particular, is there a "standard" way to generate a stable 1.65V that can sink and source 200µA current? Is TLE2141 (low noise) a good choice of op amp for the 1.65V buffer?

Circuit description: U3A permits scaling of the input up to a gain of 4. The maximum output from U3A will be 10V peak-to-peak. U4 is a differential amplifier that scales down this input to with an attenuation of 3.3V/10V (as you can see, in simulation, a 6.86Vpk-pk input gives a 3.21Vpk-pk at the output). the purpose of U5 is to supply a bias voltage of 1.65V with a bit of adjustability to trim out any system offset error. The bias is independent of the gain of U4.

Final question. I've gone for a non-inverting amplifier for U3. Is there any advantage of using an inverting amplifier in that position instead? I'm trying to minimise noise and maintain stability.

Thank you.

  • Hello D B17,

    In general, your circuit looks to do what you intend.

    There is something a bit confusing about the TLC2272 U3A stage that you can help clarify. The stage has a gain of +4 V/V  and there is the Vin note about Max +3.5 V, Min -3.5 V. Is that the intended input voltage range, or output voltage range? If we assume that is the output range, then the maximum input U3A input voltage would be +/-0.875 V. Otherwise, if the input voltage gets much larger the output will clip.

    I went ahead and set up your circuit in our TINA simulator. The input is +/-0.875 Vpk to U3A, with +/-3.5 Vpk out. The voltage offset of the op amps comes into play and introduce offset into the signal paths, but overall the gains through the circuit result in an output voltage of about 2.5 Vp-p centered about 1.85 V. The VM4 output, which would connect to the ADC input swings from about +0.5 V to +3.1 V. The input U3A input voltage could be increased to get a swing range closer to the desired 0 to 3.3 V, but the TLE2141 positive output limit might become an issue. There are many newer op amps that can swing much closer to the supply rails.

    Regarding your question, I've gone for a non-inverting amplifier for U3. Is there any advantage of using an inverting amplifier in that position instead? I'm trying to minimise noise and maintain stability." The TLE2141 is a unity gain stable amplifier and the RC load on the output should pose a stability issue because the 100 Ohm resistor sufficiently isolates the 330 ohm resistance from the output. There shouldn't be much phase margin degradation contributed by this load.

    I do have an idea regarding an accurate and easily applied +1.65 V reference. The REF2033 is a precision +3.3 V reference with a very useful feature. It has a Vbias output that is 1/2 the 3.3 V Vref voltage, or 1.65 V. It would provide a precise +1.65 V output an eliminate the need to adjust a potentiometer and one of the op amps.

    Regards, Thomas

    Precision Amplifiers Applications Engineering

  • Hi Thomas. Thank you for taking the time to reproduce my circuit in your simulator. I really appreciate your effort and support.

    You wrote: "There is something a bit confusing about the TLC2272 U3A stage that you can help clarify. The stage has a gain of +4 V/V  and there is the Vin note about Max +3.5 V, Min -3.5 V. Is that the intended input voltage range, or output voltage range? If we assume that is the output range, then the maximum input U3A input voltage would be +/-0.875 V. Otherwise, if the input voltage gets much larger the output will clip."

    My clarification: +/- 3.5V is the maximum value of the input to my U3A. Typically, however, the input will be less than this. I don't know for sure what the input value will be, so I need adjustable gain.

    The value +/-0.875 that you have used is quite possible. In this case, I would want to increase the gain so that I get a good dynamic range on my ADC. R1 on your circuit is 22.5K. On my circuit, the value this resistor can be varied between 3.3k and 23.3k. Please could you adjust your value of R1 to 23.3K so that our circuits match?

    (If the input to U3A has greater amplitude...say +/-2V...then I would adjust the gain of U3A to just a little bit less than +2.5V/V. TLC2272 is RRO and can swing to both supply rails so it shouldn't clip with this gain. But for now though, let's stick with an input of +/-0.875V.)

    The output from U3A will have a +/- peak value of (1 + 23.3/7.5)*0.875V and a centre of 0V. You add a bias of 1.65V in your circuit. But your output VM4 has a bias of 1.84V. This is confusing me.... U4 is a differential amplifier so the added bias should be independent of the amplifier gain. Where does 1.84V come from?

    On your circuit, when VG1=0, VM3=0 and VM5=1.65. So VM1 = 1.65*100k/(100k + 33k) = 1.24V. But on your graph it shows VM1=1.33V. What am I missing?

    Thanks again, Thomas.

  • Hello D B17,

    Your questions:

    The output from U3A will have a +/- peak value of (1 + 23.3/7.5)*0.875V and a centre of 0V. You add a bias of 1.65V in your circuit. But your output VM4 has a bias of 1.84V. This is confusing me.... U4 is a differential amplifier so the added bias should be independent of the amplifier gain. Where does 1.84V come from?

    I checked my simulation circuit and you are correct, some of the voltage levels such as the 1.84 V doesn't make sense. It is too high to be caused by op amp voltage offset, or some other minor error contribution. I found that it is being caused by imperfect TLE2141 simulation models. If the 1.65 V reference buffer is disconnected from the rest of the circuit the output voltage moves to +1.65 V, which is correct.

    The TLE2141 is an older op amp and its simulation model is a simple Boyle model, dated 1990. Although state of the art at the time, models have progressed significantly since that time. I reran the simulation using a modern Precision Amplifier op amp, the OPA196. It has the latest, most sophisticated op amp model design that provides accurate results. Below, you can see how much different things are from a simulation using this modern op amp model. Do note that I changed the feedback resistor in the input gain stage to 23.3 kilohm as you requested. The schematic voltages shown in blue are for a dc simulation.

     On your circuit, when VG1=0, VM3=0 and VM5=1.65. So VM1 = 1.65*100k/(100k + 33k) = 1.24V. But on your graph it shows VM1=1.33V. What am I missing?

    You can see that with the OPA196 op amps in the circuit VM1 is now the correct +1.24 V level.

    I hope this helps.

    Regards, Thomas

    Precision Amplifiers Applications Engineering

  • That's a relief, Thomas, thank you! I'm pleased that our calculations match. Thank you for sorting it out. I will bookmark the OPA196 for future work.

    Before closing this topic, I have a subsidiary question that follows on from this. For my present project, I am restricted to DIP packages. I am going to try TL071AN in your circuit positions U2 and U3. Please may I ask if TL071AN is unity gain stable for U2 and for the differential amplifier U3?
  • Hello D B17,

    The TL071AN is unity-gain stable op amp, and the datasheet in Fig. provides an example of it connected as a unity-gain amplifier. The +1.65 V unity-gain buffer shouldn't have any issue because its output probably doesn't see more than a couple of picofarads of capacitance in the real circuit.

    When the TL071AN is applied in the differential amplifier stage its noise gain is actually greater than 1 V/V. A 330 picofarad alone might degrade the phase margin to where the stage is marginally stable, or possibly unstable. However, having the series 100 Ohm output resistor in place is effective in isolating the op amp output from the 330 pF. Little phase margin degradation should occur in that case and the stage should be stable.

    Regards, Thomas
    Precision Amplifiers Applications Engineering
  • Thanks again. I really appreciate your interest and your fast response. Have a great day!