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TPS65381 Figure 5-5. Software Flowchart … (150)

Hello,

Please answer following question from customer.

 

Please refer attached file and answer following questions.

 1526.No.150_Q&A_Syncronization_E2E.pdf

Q1:

I think WD_FAIL_CNT increment and decrement are reversed as attached file.

Please confirm if datasheet is correct.

 

Q2

Please advise why operation of “Observe WD status bits in WDT_STATUS register are not set (bits D5 to D0)” and “Observe corresponding WD status bit(s) in WDT_STATUS register is set (bits D5 to D0)” are required.

I believe if LBIST guarantee the function of “WD status bits in WDT_STATUS  register (bits D5 to D0)” it is not needed to check D5 to D0 status.

Does LBIST guarantee the function of D1 to D0 ?

 

Best Regards.

  • Toshio,

     

    This post has been assigned an apps engineer. Please allow them a few days to give you an answer to your question.

  • Is this software is able to work with mac and linux. I currently use a online diagramming solution called creately. its a good flowchart designer 

  • Hello Alex-san,

    I have not received answer.

    Could you ask apps engineer again?

     

    Best Regards.

  • Sorry for the delay. I' m looking at and will make sure to post the answer before the end of this week.

  • Hello Mahmoud-san,

    Thank you for your response.

    I would like to wait your answer.


    Best Regards.

  • Hello Mahmoud-san,

    Please send answer for my question.

    Best Regards.

  • Q1: I think WD_FAIL_CNT increment and decrement are reversed as attached file.

    [Answer] Yes, reversed.

    Please confirm if datasheet is correct.

    Q2: Please advise why operation of “Observe WD status bits in WDT_STATUS register are not set (bits D5 to D0)” and “Observe corresponding WD status bit(s) in WDT_STATUS register is set (bits D5 to D0)” are required.

     [Answer] The part of the WD service routine should include check on current WD Answer count (which is covered in WDT_STATUS register)

    I believe if LBIST guarantee the function of “WD status bits in WDT_STATUS  register (bits D5 to D0)” it is not needed to check D5 to D0 status.

     [Answer] Yes. Anyway, as part of sequencing by MCU, it can track that WD Answer count is being updated as well (as another confirmation WD related SPI command has been recognized as a valid and was processed by device.

    Does LBIST guarantee the function of D1 to D0 ?

    [Answer] It covers related circuit as well.

  • Hello Mahmoud-san,

    Thank you for your answer.

    According your answer I can’t understand why “Procedure B” of attached file is required. MCU sent 4 answers and “Procedure A” checked if WD answer sequence & timing is correct. “Procedure B” performs same flag check with “Procedure A” so I believe “Procedure B” is not required.

     7446.No.150_Q&A_Syncronization_E2E_2.pptx

    Please advise the purpose of “Procedure B”.

    (For example, “Procedure B” tests if WD status flags are working correct for both correct answer and in-correct answer. But LBIST cover the WD status flags so I can’t explain the purpose of “Procedure B” to Customer.)

     

    Best Regards.

  • Hello Mahmoud-san,

    Please asnwer for my additional question.

    Best Regars.

  • Hello Mahmoud-san,

    Please asnwer for my question.

    Best Regars.

  • Hello Mahmoud-san,

    Please asnwer for my question.

    Best Regars.

  • This box is not mandatory, it depends on how many times you need to monitor the watchdog.  Decrementing only one time may not be good enough to validate watchdog function.  You may want to observe it more multiple times to observed multiple failures that will cause the watchdog fail counter to incement such as:  timeout, "bad" answer, "bad" sequence, etc.

    This is the background for this proceedure.

    - Scott

  • Hello Scott-san,

     

    1)    You said “Decrementing only one time may not be good enough to validate watchdog function.”.

            Please advise why only one time may not be good enough.

    2)    BIST covers the WD function including WD error flags so customer think no need to check the function of WD error flags in procedure B and no needs of procedure B.

          Is this correct?

     

    Best Regards.

  • A1)  This is recommened as a way to balance and manage faster fault response times and free up SPI bandwidth.  If you decrement all the way to 0 then you would need to accumulate 5 faults till power stages are disabled and another 3 faults until the RESET.  The balance is system level fault response time dependent.  By setting up the watchdog with the recommended function you are checking continuously the timing functions within the MCU that also releate to other timing critical paramters, for example MCU PWM control outputs for external power stages.

    A2)  The main reason for this recommendation of this proceedure is not to check the error flags, but to keep the error counter, clock accuracy and SPI bandwidth in balance and increases the coverage of both the MCU and TPS65381. 

    - Scott

  • Hello Scott-san,

    Thank you very much for your answer.

     

    I read your answer but I can’t understand your explanation why Procedure B (refer attached file on Aug 12 2014) is recommended.

     

    For example, you explain ”If you decrement all the way to 0 then you would need to accumulate 5 faults till power stages are disabled and another 3 faults until the RESET.” but Procedure B is in DIAGNOSTIC state and title in the flowchart is “Confirm WD function” so WD_RST_EN should be “0” not to assert RESET.

    Also I can’t understand SPI bandwidth explanation in spite of “Confirm WD function” is in DAGNOSTISTATE.

     

    Could you please explain again why you recommend to perform “Confirm WD function” in DIAGNOSTIC state.

     

    Best Regards.

  • Hello Scott-san,

    Please answer for my question posted on Oct 23 2014.

    Best Regards.

  • The decision to confirm (check) proper system WD functionality is a customer and application choice.  We recommend to do it (while in diagnostics) to validate proper watchdog system operation before going to active state.  This is a recommendation, not mandatory. 

    The second comments is once the WD is verified, options to balance the system response of the WD and timing.  The behavior of the device is dependent on the WD_FAIL_CNT.  After reset the WD_FAIL_CNT will be set at 5, which disables the driver output (ENDRV pin).  If you use the WD and decrement the counter all the way to 0 then the system fault response time to shut off the driver again after enabling ENDRV will be 5 failures of the WD which will once again have the WD_FAIL_CNT being 5 and disabling ENDRV.  The WD will need to fail another 3 times until the WD_FAIL_CNT hits 7 + 1 and causes the RESET to happen when WD_RST_EN is set.  Depending on the WD time set by the customer this may be too long for the system response time.  There are two ways to balance this:  manage the WD_FAIL_CNT to some level between 0 and 5 and keep the WD time long so you need fewer SPI writes (overhead) while keeping the time to disable and reset lower, or decrease the WD time which will increase the number of SPI writes needed in a given period of time (using all the SPI bandwidth only to run the WD).

    - Scott