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Electrical characteristics of ADS1115-Q1

Other Parts Discussed in Thread: ADS1115

I confirmed a data sheet, but there is not mention of the following item.

Please tell me the following parameter.

  Differential Nonlinearity(DNL)

  Total Harmonic Distortion(THD)

  Signal to Noise and Distortion(SINAD)

  Spurious Free Dynamic Range(SFDR)

  Hysteresis of Schmitt trigger inputs(VHYST)

  Pin capacitance(all inputs/outputs)(CIN,COUT)

  Bus Capacitance(CB)

  • Sato-san,

    A few of the parameters are more related to high-speed ADCs (pipeline-architecture), so THD, SINAD and SFDR are typically not specified for precision-ADCs (SAR- and Delta-Sigma-ADCs) like the ADS1115.

    The DNL is not explicitly specified, but since it's rated for "no missing codes", it is less than one LSB.

    I'll attempt to find out about the remaining parameters.

    BR,

    Frank

  • Sato-san,


    Frank is correct in that many of these parameters of THD, SINAD, and SFDR are more appropriate for higher speed ADC. Many of the these Delta Sigma ADCs are closer to DC and have a significant drop in frequency response (look at the frequency response of the part in the datasheet in Figure 21).

    For the DNL, again as Frank mentioned, it is likely much less than 1 LSB.

    The pin capacitance and the bus capacitance are likely to be somewhere between 0.5pF and 5pF. If you want, you can look at the IBIS model, and find that typical values are between 1 and 2 pF when you include the C_Comp and package capacitance in the model. Note that for the bus capacitance, the trace capacitance on the board is likely to be much larger than the capacitance contributed by the device.

    I don't think the digital input Schmitt trigger were characterized, but I did find that the logic level transition high typical threshold is about  0.49 x VDD, while the logic level transition low is typically 0.35 x VDD.

    Joseph Wu

  • Incidentally the IBIS model can be found here:

    http://www.ti.com/lit/zip/sbam025

    Joseph Wu