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PGA450-Q1 Implementation

I have played around with the PGA450 Dev kit and it looks like it could certainly do the job we would like it to do. But I have been having troubles finding all the appropriate docs on the TI site. There seems to be multiple versions of firmware, GUI programs, and application docs strewn across the forums, but not in one centralized place with the latest and greatest of everything available. I also saw some references to some example application firmware but the only stuff I have been able to find is how to initialize the registers and a reference to an empty design note. Is there a way I can get my hands on these things to further investigate this chip?

I am also curious how we are expected to accurately process the signal that is captured in the FIFO. Is it feasible to do all the processing we need to on just the 8051 micro.

Is there a reasonable way to take the DAC output and perhaps process it only in HW? I can take care of a pulse train and threshold triggering, but the initial signal that is sent out seems to be very tricky to deal with. Is there a reliable way with the blanking timer or maybe a FIFO offset to make the DAC output only the start of the response signal?

I have a few other questions in mind as well, but maybe this isn't the best place to ask them...

Thanks

  • Ryan,

    For now, I can send you the documentation to you individually.  Soon we will have more of this information available on the web so that in the future it will be easy to find the reference documentation.

    It is feasible to do all of the signal processing on the 8051 micro.  The digital datapath processes the signal so that the echo amplitude is what is finally stored in the FIFO.  You should find that any additional processing can be handled by the 8051 micro.

    Typically the DAC is just used for debugging purposes, so I'm not sure how it responds to the blanking timer.  What the blanking timer does is delay the start of storing the digital data to the FIFO.

    -Clancy  

  • Thank you for the response, I believe I found most of the documents that are online, but it would be great to take a look at what you have as well.

    I see now that the firmware examples I had were doing everything in the ISRs, I hadn't looked quite closely enough. I will have to get a compiler that will work for this so that I can play with things a bit more.

    I guess I assumed that DAC was just outputting the FIFO directly, but the blanking timer does not affect the DAC it seems. The blanking timer does work as expected on the Eval Monitor, so that gives me a better idea of what I could do with this.

    We are likely going to have 2-3 sensors in this application on the same PCB with no central MCU, would it be feasible to switch the I/O of a single PGA450 to multiple transformers (likely with the GPIO and a decoder), or would a better approach be to use multiple PGA450s and synchronize them somehow?

    It also looks like the Serial Rx/Tx lines could be usable as GPIO lines, is this doable?