Hello,
Q1: Behavior of CFG_CRC_EN
Datasheet P58 explains as follows.
”When enabled, the CRC check on the configuration registers is performed permanently.”
I tested behavior of CFG_CRCR_ERR bit using EVM and result is as follows.
1) Set CFG_CRC value that cause CFG CRC error in DIAGNOSTIC state.
2) Set CFG_CRC_EN=1 and CFG_CRC_ERR is changed to “1”
3) Changed Configuration register(for example WD_WIN1_CFG) to pass CFG CRC check, but CFG_CRC_ERR didn’t change to “0”.
I think CFG_CRC_ERR bit changed to “0” if CFG CRC check is performed permanently(continuously) as explained in datasheet.
Please advise if CFG CRC check is performed continuously while CFG_CRC_EN=1, or CFG CRC check is performed once when CFG_CRC_EN set to “1” and I need to change CFG_CRC_EN “0” to “1” again to perform CRC check again.
Q2: Behavior when EE_CRC_ER=1
Datasheet has following explanations about behavior of EE_CRC_ERR and state change to SAFE.
<P58>
In case of a detected checksum error with the TPS65381-Q1 device in DIAGNOSTIC state, clearing bit CFG_CRC_EN to 0 brings the TPS65381-Q1 device into SAFE state (the ENDRV pin is pulled low).
<P60>
In case of a detected signature error in the configuration registers, the device reports an EEPROM signature error when the CFG_CRC_EN bit in the SAFETY_CHECK_CTL register is set to 0 first before performing the EEPROM CRC check by setting the EE_CRC_CHK bit in the SAFETY_BIST_CTRL register to 1, even when the EEPROM bits do not have an error.
According above explanation, when CFG_CRC_EN is set to “0” while CFG_CRC_ERR=1 in DIAGNOSTIC state, EE_CRC_ERR is set “1” and transition to SAFE state.
Please advise if TPS65381 transition to SAFE state or not, in case of EE_CRC_ERR is caused by EEPROM bits error in DIAGNOSTIC state.
Best Regards.