TPS65381 CFG CRC Check and EEPROM CRC Check(No.170/171)

Toshio,

 

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Hello Alexander-san,

Please answer my question.

Best Regards.

Hello,

Please answer my question.

Best Regards.

Hello,

Please answer Q1.

Please close Q2, because I found answer in datasheet and TPS65381 transitions to SAFE state.
<Page 74>
This bit is set to 1 when the calculated CRC8 value does not match the expected CRC8 value stored in the EEPROM DFT register. When this bit is set to 1 and device is in the DIAGNOSTIC state, the device transitions to SAFE state.

Best Regards.

Hello,
Please answer following original my question.

Q1: Behavior of CFG_CRC_EN
Datasheet P58 explains as follows.
”When enabled, the CRC check on the configuration registers is performed permanently.”

I tested behavior of CFG_CRCR_ERR bit using EVM and result is as follows.
1) Set CFG_CRC value that cause CFG CRC error in DIAGNOSTIC state.
2) Set CFG_CRC_EN=1 and CFG_CRC_ERR is changed to “1”
3) Changed Configuration register(for example WD_WIN1_CFG) to pass CFG CRC check, but CFG_CRC_ERR didn’t change to “0”.

I think CFG_CRC_ERR bit changed to “0” if CFG CRC check is performed permanently(continuously) as explained in datasheet.

Please advise if CFG CRC check is performed continuously while CFG_CRC_EN=1, or CFG CRC check is performed once when CFG_CRC_EN set to “1” and I need to change CFG_CRC_EN “0” to “1” again to perform CRC check again.

Best Regards.

Hello,

 

Please answer my question I posted on Jan 20, 2015.

 

Best regards.

Hello,

 

Please answer my question I posted on Jan 20, 2015.

 

Best regards.

Hello,

Please answer my question.

I have to answer to customer tommorow.

Best Regards.

 

Hello,

 

Please answer for my question I posted on Jan 20, 2015.

 

Best Regards.

Hello Alexander-san,

It passed long time from Nov 5 2014.
Please ask apps engineer to answer my question.

Regards.

Ushikubo-san,Sorry for the delay. I will escalate this post.

Hi Ushikubo-san,

Sorry for the delay, I had discussed this and another CRC question with Tsuji-san in November and I though he followed up to clarify on this.

Please confirm you are doing the following with the EVM:
1) Getting to diagnostic state
2) calculating the CRC but loading a wrong CRC value to SAFE_CFG_CRC (command 0x31 without parity) via low level SPI control
3) enabling CFG_CRC_EN via the GUI -> seeing CFG_CRC_ERR being set
4) changing a Config register which should then cause CRC to pass (ie pre-calculated CRC which would meet that stored in SAFE_CFG_CRC.
5) CFG_CRC_ERR remains 1, you are expecting this to auto update and clear but it didn't.

Did you check if the device changed state in this process. Could you share the exact steps you did so we can try to exactly duplicate it in our lab.

I tried to test this using a slightly different approach:

1) power up and go to diagnostic via IGN, use auto update and autoset DIAG EXIT MASK
2) use the "Calc. CRC" button which calculated correct CRC to be 100 decimal (0x64 hex), this also set the CFG CRC EN bit and there the CFG CRC ERR bit is cleared so there is no CRC error.
3) Use SPI control to read 0x2d (SAFE_CFG_CRC) and it is 0x64.
3) Use SPI control to write 0x31 (SAFE_CFG_CRC) to 0x63 which should cause a CRC error. I did not see CFG CRC ERR update in the GUI. Manually read SAFETY STAT 2 register, and CFG CRC ERR is not set.
4) Use the GUI and clear the CFG CRC EN button in the Safety Check Control box --> no change to CFG CRC ERR
5) Use the GUI and set the CFG CRC EN button in the Safety Check Control box --> CFG CRC ERR is set.

I will have to discuss with our systems engineer if the continual checking of the CRC only starts when the device is transitioned to active state. In the meantime please send your exact steps of testing this so we can also try it on an EVM here.

Thanks,
Scott

Hello Scott-san,
Thank you for your reply.

Following is my exact steps of testing this using EVM.
1) Power up and go to diagnostic via CANWU, use auto update and auto set DIAG EXIT MASK.
2) Use the "Calc. CRC" button and calculated correct CRC is 106 decimal (0x6a hex).
CFG_CRC_EN is set and CFG_CRC_ERR is not set.
3) Use SPI control to write 0x31 (SAFE_CFG_CRC) to 0x6b which should cause a CRC error.
But I did not see CFG CRC ERR update in the GUI.
4) Use GUI and clear CFG_CRC_EN and set CFG_CRC_EN again.
I see CFG CRC ERR is set.

I think I need to toggle CFG_CRC_EN (set -> clear -> set) to update CFG CRC ERR in DIAGNOSTIC state.
And your EVM result is same with my experience.

Please check if behavior is same in ACTIVE state or not.

Best Regards.

Hi Ushikobo-san,

I have tried your set up and see the same behaviour.  There is no way to directly check the ACTIVE state since the registers that are checked by the CRC as well as the SAFE_CFG_CRC cannot be written outside of diagnostic state.  I have done some indirect experiements for ACTIVE state and I am in discussion with our design team on this topic. 

I should be able to give more update on the topic next week after more work with the design and systems team. 

-Scott