Question about TPS65381-Q1 SAFETY_ERR_STAT Register

masahiko shimizu

Guru 11235 points

Hi,

Regarding the following bits in SAFETY_ERR_STAT register,

SAFETY_ERR_STAT/D[5] ERROR_PIN_FAIL
SAFETY_ERR_STAT/D[4] WD_FAIL
SAFETY_ERR_STAT/D[3:0] DEV_ERR_CNT[3:0]

in the description about these bits , they'll be cleared to 0 after SPI WR access.

does it mean that they'll be cleared to 0 after SPI WR access to any register?

or cleared to 0 after only SPI WR access to particular register ?

Thanks,

Shimizu

over 9 years ago

0 Scott Monroe over 9 years ago

TI__Mastermind 20580 points

Hi Shimizu-san,

I believe this should be a SPI WR to the specific register, but I'm checking with the system team on this. Please give use several days. We cannot check it with the GUI since it is real time and with the faults we would end up resetting the device and causing the failure again before we could confirm 100%.

-Scott

0 masahiko shimizu over 9 years ago in reply to Scott Monroe

Guru 11235 points

Hi Scott

Thank you for your support.

Any update on this?

Thanks

Shimizu

0 Samir Camdzic over 9 years ago in reply to masahiko shimizu

TI__Prodigy 100 points

Hello Shimzu-san,

SAFETY_ERR_STAT/D[5] ERROR_PIN_FAIL
SAFETY_ERR_STAT/D[4] WD_FAIL
SAFETY_ERR_STAT/D[3:0] DEV_ERR_CNT[3:0]

SAFETY_ERR_STAT register bits are cleared after SPI write command to SAFETY_ERR_STAT register (WR_SAFETY_ERR_STAT SPI command + SPI write data 0x00).

Regards,

Samir

0 masahiko shimizu over 9 years ago in reply to Samir Camdzic

Guru 11235 points

Hi Samir-san

Thank you for your support.

I understood.

Thanks

Shimizu

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Question about TPS65381-Q1 SAFETY_ERR_STAT Register