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TPS65381-Q1 DIAG_MUX_SEL Register

masahiko shimizu
Guru 11235 points
Other Parts Discussed in Thread: TPS65381-Q1

Hi

 Is the DIAG_MUX_SEL Register  reset by setting MUX_CFG (Bit 0,1 of DIAG_CFG_CTRL Register)?

 I write something of value to DIAG_MUX_SEL Register . then I set MUX_CFG.

 I check this register by read DIAG_MUX_SEL Register. This value is 0（none）.  

Thanks

shimizu

  • 0
    TI__Mastermind 24740 points

    I' m not sure if I understood the question. Here are the congiguration for MUX_CFG [1:0]: Diagnostic MUX

    00: The MUX output is controlled by MUX_OUT bit (bit 5 in DIAG_CFG_CTRL register)

    01: Digital MUX mode

    10: Analog MUX mode

    11: Device interconnect mode (input-pins interconnect test)

  • 0 in reply to Mahmoud Harmouch
    Guru 11235 points

    Hi Mahmoud-san

     Thank you for your support.

     and I'm sorry. I rewrite my question. 

      Is DIAG_MUX_SEL Register reset by setting MUX_CFG (Bit 0,1 of DIAG_CFG_CTRL Register)?

      At first, I set value of 10(Analog MUX mode)  to MUX_CFG.

      Next,  I set value of 0x80  to DIAG_MUX_SEL Register.

      Then, I set value of 10(Analog MUX mode) to MUX_CFG again.

      The last, I read DIAG_MUX_SEL Register. This value is none(0x00).

      Initial value of DIAG_MUX_SEL is 0x00.

      I confirmed by EVM of TPS65381-Q1.

     

     Reason of this question is my customer has issue of the read buck check at DIAG_MUX_SEL register.

     They confirmed that it is different of the wrote value and the read value at DIAG_MUX_SEL register.

    　I am looking for the reason of this behavior.

     

    Thanks

    Shimizu 

  • 0 in reply to masahiko shimizu
    TI__Mastermind 20580 points

    Hi Shimuzi-san,

    Does this only happen with the DIAG_MUX_SEL is 0x80 which is the buffered band gap.  If you overload it during monitoring you may be collapsing the bandgap which may be resetting the device.

    Did you see the same behavior with other signals on AMUX output?

    - Scott

  • 0 in reply to Scott Monroe
    Guru 11235 points

    Hi Scott-san,

     

     Thank you for your support.

     I could confirm all of AMUX signal on the EVM GUI.

     

    Thanks

    Shimizu 

  • 0 in reply to Scott Monroe
    TI__Mastermind 20580 points

    Hi Shimuzi-san,

    What you are seeing is a side effect of the way the GUI writes SPI commands for DIAG_MUX_SEL and MUX_CGF if you use the preset buttons to make the choices.  I used the GUI with the button choices and noticed when you click on MUX EN it did SPI Write (in the lower left of the GUI window) of Write Command 0x66 with data 0x82 followed by Write command 0x64 with data 0x00.  This basically enabled the AMUX (because that was the mux that was selected in the GUI pull down at the time) and set the DIAG_MUX_SEL to 0x00 in one press of the GUI.  I did an extended run using the GUI with the buttons and pull downs and noticed that every time you use the MUX EN command it will always immediately write data 0x00 into the DIAG_MUX_SEL (0x64 command).

    However if you use the SPI Write and Read commands directly and write the sequence you described the DIAG_MUX_SEL remains as you would expect and it is not reset.

    Thus the GUI sort of does a "reset" on this register due to the way the software of the GUI works.   

    - Scott