Hi
My customer is using TPS65381-Q1.
I have a question.
Could you let me know the following deference of this EVM behavior and datasheet?
The suggestion of WD_ERR and MCU_ERR in datasheet is the following.
- "Cleared to 0 after SPI read access and if bit ERROR_PIN_FAIL in SAFETY_ERR_STAT is cleared"
- "Cleared to 0 after SPI read access when watchdog fail counter is less than 7"
I confirmed at TPS65381-Q1EVM with removing Auto update function of EVM and at masking DIAG_EXIT_MASK(=1).
I start EVM, and then ERROR_PIN_FAIL, WD_FAIL, MCU_ERR and WD_ERR is set for DIAG mode time out.
Next, I clear ERROR_PIN_FAIL, WD_FAIL. and I read ERROR_PIN_FAIL and WD_FAIL.
ERROR_PIN_FAIL and WD_FAIL were also cleared.
I think that "Cleared to 0 after SPI read access" means the following.
1. Clear bit ERROR_PIN_FAIL and WD_FAIL.
2. Read WD_ERR and MCU_ERR -> 1 value is read.
3. Read WD_ERR and MCU_ERR again -> 0 value is read.
Is this behavior the cause of DIAG mode time out at masking DIAG_EXIT_MASK(=1)?
or my misunderstanding of datasheet?
Thanks
Shimizu
